[求助]伪随几序列 序列, 求助

guojunfen1982

我有伪随机序列的产生程序,老师让我嵌入分频器,该怎么办啊

guojunfen1982

我用得是m序列, 我不小心写错字了随机

guojunfen1982

Library ieee;
Use ieee.std_logic_1164.all;
Entity ps7 is
Port(clk:in std_logic;
Load:in std_logic;
Qut std_logic
);
end ps7;
architecture behav of ps7 is
signal c0,c1,c2,c3,c4,c5,c6,c7:std_logic;
begin
process(clk,load)
begin
if clk’event and clk=’1’ then
if(load=’1’)then
c7<=’0’;
c6<=’0’;
c5<=’0’;
c4<=’0’;
c3<=’0’;
c2<=’0’;
c1<=’0’;
c0<=’1’;
Q<=c7;
ELSE
C1<=c0;
C2<=c1;
c3<=c2;
c4<=c3;
c5<=c4;
c6<=c5;
c7<=c6;
c0<=c7 xor c4 xor c3 xor c2;
Q<=c7;
end if;
end if;
end process;
嵌入分频器可得到想要得频率进行仿真

guojunfen1982

谢谢你，可我现在还没有头绪，越做越迷糊，EDA你学得很好是吗，我毕业设计要用真麻烦，不管怎样还是要谢谢你

guojunfen1982

我是要在伪随机序列的程序里嵌入一个分频器的程序,具体的我不清楚,我去问问老师吧,可老师好象也不懂啊
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clk_div IS
PORT(clk :IN STD_LOGIC;
clk_div2 :OUT STD_LOGIC;
clk_div4 :OUT STD_LOGIC;
clk_div8 :OUT STD_LOGIC;
clk_div16 :OUT STD_LOGIC);
END clk_div;
ARCHITECTURE rtl OF clk_div IS
SIGNAL count :STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk ='1') THEN
IF (count ="111111") THEN
Count <= (OTHERS=>'0');
ELSE
Count <= count+1 ;
END IF;
END IF;
END PROCESS;
Clk_div2 <= count(0);
Clk_div4 <= count(1);
Clk_div8 <= count(2);
Clk_div16 <= count(3);
Clk_div32 <= count(4);
Clk_div64<= count(5);

END rtl;
这是我在网上下的关于基于CPLD的64分频器的设计,可它们能结合有关系吗?
五一快到了,希望过的愉快
[em13]

guojunfen1982

我知道了,我也是刚明白,谢谢了,我先自己做做

guojunfen1982

Library ieee;
Use ieee.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
Entity ps7 is
Port(clk:in std_logic;
i,u,n:in std_logic;
Load:in std_logic;
Qut std_logic;
yut std_logic
);
end ps7;
architecture behav of ps7 is
signal c0,c1,c2,c3,c4,c5,c6,c7:std_logic;
signal d,c,b,a:std_logic;
signal count_4:std_logic_vector(3 downto 0);
signal k:std_logic_vector(7 downto 0);
begin
process(clk,load)
begin
if clk'event and clk='1' then
if(load='1')then
c7<='0';
c6<='0';
c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='0';
c0<='1';
Q<=c7;
ELSE
C1<=c0;
C2<=c1;
c3<=c2;
c4<=c3;
c5<=c4;
c6<=c5;
c7<=c6;
c0<=c7 xor c4 xor c3 xor c2;
Q<=c7;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(count_4="1111") then
count_4<="0000" ;
else
count_4<=count_4+1;
end if;
end if;
end process;
D<=count_4(0);
c<=count_4(1);
b<=count_4(2);
a<=count_4(3);
begin
k<=i & u & n;
process(k)
begin
case k is
when"000"=> y<=clk;
when"001"=> y<=d;
when"010"=> y<=c;
when"011"=> y<=b;
when"100"=> y<=a;
when others=> y<=clk;
end case;
end process;
end behav;

这是我的程序蓝颜色是出问题的地方，是cpld那有三个按键，000表示无键按下输出原频率，001有一个键按下实现二分频，以此类推，可编译有错误，我也觉得不太对，该怎么改呢？

guojunfen1982

谢谢，我查出错误了，昨天太粗心了，我仿真出结果了，可我在程序里通过设置i，u，n的值就直接分频了，怎么不需要外围电路呢，是不是还需要一个判断键是否按下的程序呢