一个让ISE8.1虾米的模块，不信你试试？
说来也奇怪
简简单单的一个序列监测器，功能就是监测电路连续的三个高电平。
在Mentor Precision、Synplicify Pro、QuartusII5.1里顺利综合通过，网表正确显示；
唯独ISE编译综合得驴唇不对马嘴，结果的RTL图和元件图看了令人崩溃。
你们试试，看看是怎么回事？最后生成的的电路图明显错误。
module Seq_Rec_3_1s_Moore (D_out, D_in, En, clk, reset);
output D_out;
input D_in, En;
input clk, reset;
parameter S_idle = 0; // One-Hot
parameter S_0 = 1;
parameter S_1 = 2;
parameter S_2 = 3;
parameter S_3 = 4;
reg [2:0] state, next_state;
always @ (negedge clk)
if (reset == 1) state <= S_idle; else state <= next_state;
always @ (state or D_in) begin
case (state)
S_idle: if ((En == 1) && (D_in == 1)) next_state = S_1; else
if ((En == 1) && (D_in == 0)) next_state = S_0;
else next_state = S_idle;
S_0: if (D_in == 0) next_state = S_0; else
if (D_in == 1) next_state = S_1;
else next_state = S_idle;
S_1: if (D_in == 0) next_state = S_0; else
if (D_in == 1) next_state = S_2;
else next_state = S_idle;
S_2, S_3: if (D_in == 0) next_state = S_0; else
if (D_in == 1) next_state = S_3;
else next_state = S_idle;
default: next_state = S_idle;
endcase
end
assign D_out = (state == S_3); // Moore output
endmodule
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