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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Rams is
Port (
Writeen : in std_logic;
Wclk : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Addr : in std_logic_vector(3 downto 0)
);
END Rams;-- Entity Ends
Architecture Behave of Rams is
Type Mem is array ( 15 downto 0) of std_logic_vector( 7 downto 0);
Signal Memory : Mem;
Begin
Write_Process : Process(Wclk)
Begin
if (Wclk'event and Wclk = '1') then
if ( Writeen = '1') then
Memory(Conv_Integer(Addr)) <= Datain;
end if;
end if;
end process; -- Write Process Ends
Dataout <= Memory(Conv_Integer(Addr));
End Behave;-- Architecture Ends |
