我的程序如下！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity example is
port(clka:in std_logic;
sw_rst:in std_logic;
dsp ut std_logic);
end example;
architecture rtl of example is
signal clk:std_logic;
signal q:std_logic_vector(7 downto 0):="00000000";
begin
clk<=clka and (not q(7));
process(clk)
begin
if(clk'event and clk='1') then
q<=q + '1';
end if;
dsp<=sw_rst and q(7);
end process;
end rtl;
现在就是在用手动复位sw_rst 为低的时候dsp要有足够的延时，这个我就不会做了！
[此贴子已经被作者于2003-8-28 18:20:53编辑过] | 
