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When one speaks of a DSP chip, one perceives of an off-the-shelf chip from, say, Analog Devices or Texas Instruments, which has an architecture designed to efficiently execute math-intensive DSP algorithms. And that is appropriate, as they are the most utilitarian chips for a wide range of DSP functions. Two basic DSP chip types are fixed-point and floating point.
The latter is preferred when its higher precision or dynamic range is needed, but mostly for its ease of programming. However, fixed-point DSPs are smaller and less expensive, and will almost always be used in really high volume applications. Then there are DSP chips with onboard accelerators to address heavy-duty video and image processing; these are usually called media processors.
But there are several other chip types and chip combinations that are better choices for specific DSP implementations. For example, FPGAs coupled with DSPs have been employed in high volume for cellular base stations, with the FPGA providing the heavy lifting through a hundred or more multipliers, instead of the two or four that are in the DSP that they boost. This application still warrants a vigorous market for both DSPs and FPGAs in a clearly symbiotic relationship. However, FPGAs increasingly offer standalone DSP functionality through their own RISC cores coupled with their onboard DSP math and memory features.
Although hard RISC cores embedded in FPGAs have advantages, our perception at Forward Concepts is that soft cores, such as Neos II from Altera and MicroBlaze from Xilinx, are proving more popular for DSP applications. Designers use FPGAs mainly for high-speed logic and consider control as secondary. Although the soft RISC is no speed demon compared to a hard RISC chip, soft cores are often more than sufficient for control code. But not everyone agrees.
From our interviews, we perceive that it is often less expensive to simply buy a standalone RISC chip and attach it to an FPGA. One response we got from our recent DSP survey may be telling: “Embedded CPU hard cores in FPGAs are a waste of real estate; area better employed as FPGA fabric.”
Nevertheless, FPGAs are not the only logic-array engines used to execute DSP algorithms. There are an increasing number of massively parallel processors on the market for DSP applications, some of which claim quick reconfigurability. Unlike FPGAs, these processors are not programmed in Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog, but rather through conventional computer coding techniques.
Aspex Semiconductor (High Wycombe, U.K.), IPFlex (Tokyo, Japan) and picoChip Designs (Bath, U.K.) are companies that fit this category. Aspex has a strong history in image processing, while IPFlex is being designed into cellular base stations, and picoChip is going into WiMAX base stations. However, being easily reconfigurable, these devices can address yet other markets. Companies such as IMEC (Lueven, Belgium), Morpho Technologies (Irvine, CA), and Silicon Hive (Eindhoven, The Netherlands) are also offering reconfigurable parallel processors as licensed cores.
As chip geometries have shrunk over the past two decades, the die area penalty for adding DSP functionality through parallel multipliers or SIMD extensions to MPUs, MCUs, and RISCs has diminished. Consequently, virtually all processors claim at least some level of DSP capability, from motor control at the low end of performance to audio and communications at the mid-level and to video at the high end.
The ASIC implementations of DSP functionality tend to employ licensed DSP cores from companies such as Ceva, LSI Logic, or StarCore. Then there are hardwired DSPs required for extreme high-speed computation, such as MPEG-4 or H.264 encoding, and they tend to be based on state machines rather than conventional DSP cores. In addition, Systems-on-Chips (SoCs) increasingly employ multiple processors, with the RISC/DSP core combos being the most popular. The combination of DSP and RISC cores on the same chip makes sense in many markets, even when a cheaper solution might be a single DSP-only or RISC-only chip. Often, the skills required for DSP implementation come from people not concerned with traditional data processing.
However, in the case of IP phones, for example, a RISC engine pairing is essential because virtually all licensable IP telephony protocols (H.323, SIP, and so on) are only available in ANSI C and are much easier to implement on a floating-point RISC platform that has a high-level operating system such as Linux or Nucleus. Consequently, traditional DSP chip companies now offer DSP/RISC combo chips for Voice over Internet Protocol (VoIP) markets and for cell phone markets as well.
In such cases, the RISC engine is better at interfacing with the user (keyboard, display, directory, handshaking protocols, and so on), while the DSP provides the communications functionality. The lesson is that DSP functionality can be had through many chip types, and one should consider that there are more devices available than just dedicated DSP chips. |
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海潮 http://blog.sina.com.cn/m/haichao |
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