|
- UID
- 130526
- 性别
- 男
|
DSP总体设计中需要注意的几点：
Data Path
The data path is the part of the processor that does all the useful work,
e.g. execution units, register fles, data memories, and buses connecting
these components. The data path design consists of mapping the instruction
set to hardware. Execution units, registers, and interconnects (buses)
are added to the architecture until there is hardware to support all instructions.
One goal is to reach the highest possible degree of multiplexing, i.e.
hardware components should be reused between as many instructions as
possible in order to minimize the total amount of hardware.
Another important issue is the pipeline design. The number of pipeline
steps must be decided and the pipeline balanced to avoid unwanted
critical paths.
Control Path
The control path is all hardware needed to generate the appropriate control
signals for the data path. This includes program memory, instruction
fetching, instruction decoding, and program fow control (logic handling
jumps, hardware loops, interrupts, pipeline hazards, etc).
While the data path constitutes the major part of the hardware, the
control path is usually the part requiring the most care in both design and
verifcation.
Memory Subsystem
Memory is a major performance bottleneck in many systems and the gap
between computing performance and memory performance keeps growing.
The access time for memory is typically longer than the critical path
applications often require a large amount of memory and a very high
memory bandwidth, making design of the memory subsystem a major
challenge. In systems requiring large amounts of memory, much design effort
is put into features such as cache control, MMUs, and advanced DMA
features. These are complex functions and a large set of possible execution
cases must be carefully veried to avoid deadlocks or data corruption.
This thesis is however mostly concerned with processors using relatively
small on-chip memories. The issue of memory subsystem design
is thereby limited to number, types, widths, and sizes of memories, bus
organization, and addressing circuitry. |
|
海潮 http://blog.sina.com.cn/m/haichao |
|
