向大家请教一个问题:
'timescale 1ns/1ns
'include "./compare.v"
module t;
reg a,b;
wire equal;
initial
begin
a=0;
b=0;
#100 a=0;b=1;
#100 a=1;b=1;
#100 a=1;b=0;
#100 a=0;b=0;
#100 $stop;
end
compare m(.equal(equal),.a(a),.b(b));
endmodule
是用Verilog HDL编的,在modelsim6.0里为什么不能仿真呢?这里的compare.v模块文件己经写好,且编译过了没有问题.
modelsim6.0的出错提示是:
** Error: F:/t_compare.v(1): near "'t": Illegal base specifier in numeric constant.
** Error: F:/t_compare.v(1): near "'t": expecting: LIBRARY CONFIG
** Error: F:/t_compare.v(1): Expecting numeric digits.
** Error: F:/t_compare.v(2): near "'i": Illegal base specifier in numeric constant.
** Error: F:/t_compare.v(2): Expecting numeric digits.
这是什么意思啊?我怎么也弄不懂.
谢谢各位了! | 
