| library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity??am is
port(
a,b :in std_logic_vector(0 downto 0);
c: out std_logic_vector(0 downto 0)??);
end;
architecture bh of am is
variable?? x,y,z : integer;
begin
x<=conv_integer(a);
y<=conv_integer(b);
z<=x+y;
c<=conv_std_logic_vector(z);
end;
在这个简单的程序中, 为什么在编译时,
C<=CONV_STD_LOGIC_VECTOR(Z)
在这里总是出错,但
x<=conv_integer(a);
y<=conv_integer(b);都能通过,
这些转换命令应该怎么用??
TO_STD_LOGIC_VECTOR();
TO_BIT_VECTOR();
TO_STD_LOGIC;
TO_BIT();
CONV_INTEGER();
CONV_UNSIGNED();
CONV_SIGNED();
CONV_STD_LOGIC_VECTOR(); |
