LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ch6_5_1 IS PORT (CP : IN STD_LOGIC; DIN: IN STD_LOGIC; OP : OUT STD_LOGIC ); END ch6_5_1;
ARCHITECTURE a OF ch6_5_1 IS TYPE STATE IS (S0,S1,S2,S3); --State Type Declare SIGNAL  resentState: STATE ; SIGNAL NextState : STATE ; BEGIN SwitchTONextStateROCESS (CP) BEGIN IF CP'event AND CP='1' THEN  resentState<=NextState; END IF; END PROCESS SwitchTONextState; ChangeStateModeROCESS (DIN,PresentState) BEGIN CASE PresentState IS WHEN S0=> IF DIN='0' THEN NextState<=S0; ELSE NextState<=S1; END IF; OP<='1'; WHEN S1=> IF DIN='1' THEN NextState<=S1; ELSE NextState<=S2; END IF; OP<='1'; WHEN S2=> IF DIN='1' THEN NextState<=S2; ELSE NextState<=S3; END IF; OP<='0'; WHEN S3=> IF DIN='1' THEN NextState<=S0; ELSE NextState<=S1; END IF; OP<='1'; WHEN OTHERS=> NextState<=S0; OP<='0'; END CASE;