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- UID
- 19245
- 性别
- 男
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| 如何在每次en为0是都先让count复位为0？？ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity samp_cnt is
Port ( samp_clk : in std_logic;
std_clk: in std_logic;
en: in std_logic;
d_in : in std_logic;
samp_out:??inout std_logic;
cnt: inout integer range 0 to 3;
count: out integer range 0 to 4;
cnt_out : out integer range 0 to 4);
end samp_cnt;
architecture Behavioral of samp_cnt is??
signal samp_out: std_logic;
signal cnt: integer range 0 to 3;
signal count: integer range 0 to 4;
begin
samp_out<=samp_clk and d_in;
sample:?? process(en,samp_clk)
variable cnt: integer range 0 to 5;??
begin
if samp_out='1' then
if en='0' then
if (samp_clk'event and samp_clk='1' ) then
if cnt<=4 then
cnt<=cnt+1;
else
cnt<=0;
end if;
end if; ????????
end if;??
end process sample;
coun: process(en,samp_out)
begin
if (std_clk'event and std_clk='1') then
if en='0' then
count<=0;
if (samp_out'event and samp_out='1') then
if count<4 then
count<=count+1;
else
count<=0;
end if;
end if;
end if;
end process coun;
cnt_out<=count;??
end Behavioral; |
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