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熟悉verilog任务用法的指教一下

熟悉verilog任务用法的指教一下

task shift_out;
  begin
    out_flag = 1;
    for(i=6;i>=0;i=i-1)
     begin
@ (negedge scl);
#`timeslice;
sda_buf = sda_buf<<1;
         end 
    @(negedge scl)  #`timeslice sda_buf[7] = 1;  //非应答信号输出
    @(negedge scl)  #`timeslice out_flag  = 0; 
  end
endtask
这个@(negedge scl)可以在任务里面用吗?
编译的时候怎么老出错啊?
那位知道? 谢谢了
eeprom.v" line 140: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 141: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 142: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 143: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 144: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 145: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 146: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 147: Unsupported Event Control Statement.
ERROR:Xst:850 - "eeprom.v" line 148: Unsupported Event Control Statement.
我这个程序是一本书上的例子,我想问时序逻辑在任务里面怎么用?
谢谢了
always @ (negedge sda)
if(scl == 1 )
begin
State = State + 1;
if(State == 2'b11)
disable write_to_eeprm;
end
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.13.276.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com
disable怎么也不可以用 啊?
State ==2'b11改成 State =2'b11
试一下
david
多了一个end
david
用task时,要有端口与类型说明,再begin,end
david
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