在Spartan-3系列FPGA中使用LUT构建分布式RAM(4)---‘连载――我与FPGA活动’” 连载

pengpengpang

前面讲了分布式RAM的方方面面，下面以RAM_16S为例，分别给出其在VHDL和Verilog HDL下面的模板代码（在ISE Project Navigator中选择 Edit--- Language Templates，然后选择VHDL 或者Verilog, 最后是Synthesis Templates --- RAM，在http://xilinx.eetrend.com/blog/776中也有具体调用过程的描述）。CORE Generator可以产生类似的代码以供行为仿真使用，它们可以在ISE Project Navigator中双击.coe文件看到。

VHDL Template Example
--
-- Module: RAM_16S
--
-- Description: VHDL instantiation template
-- Distributed RAM
-- Single Port 16 x 1
-- Can also be used for RAM16X1S_1
--
-- Device: Spartan-3 Family
--
---------------------------------------------------------------------
--
-- Components Declarations:
--
component RAM16X1S
-- pragma translate_off
generic (
-- RAM initialization (“0” by default) for functional simulation:
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
O : out std_logic
);
end component;
--
---------------------------------------------------------------------
--
-- Architecture section:
--
-- Attributes for RAM initialization ("0" by default):
attribute INIT: string;
--
attribute INIT of U_RAM16X1S: label is "0000";
--
-- Distributed RAM Instantiation
U_RAM16X1S: RAM16X1S
port map (
D => , -- insert Data input signal
WE => , -- insert Write Enable signal
WCLK => , -- insert Write Clock signal
A0 => , -- insert Address 0 signal
A1 => , -- insert Address 1 signal
A2 => , -- insert Address 2 signal
A3 => , -- insert Address 3 signal
O => -- insert Data output signal
);
--
---------------------------------------------------------------------
R
Verilog Template Example
//
// Module: RAM_16S
//
// Description: Verilog instantiation template
// Distributed RAM
// Single Port 16 x 1
// Can also be used for RAM16X1S_1
//
// Device: Spartan-3 Family
//
//-------------------------------------------------------------------
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off
defparam
//RAM initialization (“0” by default) for functional simulation:
U_RAM16X1S.INIT = 16'h0000;
// synopsys translate_on
//Distributed RAM Instantiation
RAM16X1S U_RAM16X1S (
.D(), // insert input signal
.WE(), // insert Write Enable signal
.WCLK(), // insert Write Clock signal
.A0(), // insert Address 0 signal
.A1(), // insert Address 1 signal
.A2(), // insert Address 2 signal
.A3(), // insert Address 3 signal
.O() // insert output signal
);
// synthesis attribute declarations
/* synopsys attribute
INIT "0000"
*/

          CORE Generator产生分布式RAM、同步FIFO和异步FIFO的说明文档可以分别在如下网址找到。
• CORE Generator: 分布式RAM模块
http://www.xilinx.com/ipcenter/catalog/logicore/docs/dist_mem.pdf
• CORE Generator: 同步FIFO模块
http://www.xilinx.com/ipcenter/catalog/logicore/docs/sync_fifo.pdf
• CORE Generator: 异步FIFO模块
http://www.xilinx.com/ipcenter/catalog/logicore/docs/async_fifo.pdf