DSP HPI 的引脚和时序

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苹果也疯狂发表于 2014-6-16 13:18 | 只看该作者

DSP HPI 的引脚和时序

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TMS320C620x/C670x HPI
The HPI provides 32-bit data to the CPU with an economical 16-bit external
interface by automatically combining successive 16-bit transfers. When the
host device transfers data through HPID, the DMA auxiliary channel accesses
the CPU’s address space.
The
16-bit data bus, HD[15−0], exchanges information with the host. Because
of the 32-bit-word structure of the chip architecture, all transfers with a host
consist of two consecutive 16-bit halfwords. On HPI data (HPID) write
accesses, the HBE[1−0] byte enables select the bytes to be written. For HPIA,
HPIC, and HPID read accesses, the byte enables are not used. The dedicated
HHWIL pin indicates whether the first or second halfword is being transferred.
An internal control register bit determines whether the first or second halfword
is placed into the most significant halfword of a word. For a full word access,
the host must not break the first halfword/second halfword (HHWIL low/high)
sequence of an ongoing HPI access.

The two data strobes (HDS1 and HDS2), the read/write select (HR/W), and the
address strobe (HAS) enable the HPI to interface to a variety of industry-standard
host devices with little or no additional logic. The HPI can easily interface to hosts
with a multiplexed or dedicated address/data bus, a data strobe and a read/write
strobe, or two separate strobes for read and write.
The HCNTL[1−0] control inputs indicate which HPI register is accessed. Using
these inputs, the host can specify an access to the HPIA (which serves as the
pointer into the source or destination space), HPIC, or HPID. These inputs,
along with HHWIL, are commonly driven directly by host address bus bits or
a function of these bits. The host can interrupt the CPU by writing to the HPIC;
the CPU can activate the HINT output to interrupt the host.
The host can access HPID with an optional automatic address increment of
HPIA. This feature facilitates reading and writing to sequential word locations. In
addition, during an HPID read with autoincrement, data is prefetched from the
autoincremented address to reduce latency on the subsequent host read
request.
The HPI ready pin (HRDY) allows insertion of host wait states. Wait states may
be necessary, depending on latency to the point in the memory map accessed
via the HPI, as well as on the rate of host access. The rate of host access can
force not-ready conditions if the host attempts to access the host port before any
previous HPID write access or prefetched HPID read access finishes. In this
case, the HPI simply holds off the host via HRDY. HRDY provides a convenient
way to automatically adjust the host access rate to the rate of data delivery from
the DMA auxiliary channel (no software handshake is needed). In the cases of
hardware systems that cannot take advantage of the HRDY pin, an HRDY bit
in the HPIC is available for use as a software handshake.

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