LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LS373 IS
PORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
OE:IN STD_LOGIC;
LE:IN STD_LOGIC
);
END LS373;
ARCHITECTURE ONE OF LS373 IS
SIGNAL Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(LE,OE,D)
BEGIN
IF OE='0' THEN
IF LE='1' THEN
Q_TEMP<=D;
END IF;
ELSE Q_TEMP<="ZZZZZZZZ";
END IF;
END PROCESS;
Q<=Q_TEMP;
END ONE;
下面是RTL 
[此贴子已经被作者于2008-12-26 10:23:31编辑过] | 
