Verilog对WM8731的I2S数据格式 （转载） system

pengpengpang

原文：http://blog.sina.com.cn/s/blog_73f55d0e010120iz.html//=============================================================================//  SEND_DATA_TO_WM8731.v//  one time send 24 bits data;//  READ_EN and READ_SYNC as a signal use to get data from RAM or FIFO.//=============================================================================//system clock = 50MHz`timescale 1ns/1nsmodule SEND_DATA_TO_WM8731(  CLK,  RST,  DATA_SOURCE,   BCLK,  READ_SYNC,  READ_EN,  DACLRC,  DACDAT  );input  CLK;input  RST;input [23:0] DATA_SOURCE;output  BCLK;output  READ_SYNC;output  READ_EN;output  DACLRC;output  DACDAT;reg  BCLK;reg  READ_EN;reg  READ_SYNC;reg  DACLRC;reg  DACDAT;wire [23:0] DATA_SOURCE;reg  CNT;  //BLCK >= 50 nsreg [5:0] CNT_BCLK;reg  NEWBCLK;reg [23:0] DATABUF;// DIV system clock to BCLKalways @(posedge CLK or negedge RST)begin if(!RST) begin  CNT <= 1'b0;  NEWBCLK <= 1'b0; end else if(CNT==1'b1) begin  CNT <= 1'b0;  NEWBCLK <= ~NEWBCLK; //DIV clock end else  CNT <= CNT + 1'b1;end// BCLKalways @(posedge CLK or negedge RST)begin if(!RST) begin  BCLK <= 1'b0;  READ_SYNC <= 1'b0; end else begin  BCLK <= NEWBCLK;  READ_SYNC <= NEWBCLK; //read synchronization endend// DACLRC counteralways @(negedge BCLK or negedge RST)begin if(!RST)  CNT_BCLK <= 6'b0; else if(CNT_BCLK == 6'b11_1111)  CNT_BCLK <= 6'b0; else  CNT_BCLK <= CNT_BCLK + 1'b1;end// left channel ,right channelalways @(negedge BCLK)begin if((CNT_BCLK>=0)&&(CNT_BCLK<=31))   DACLRC <= 1'b0; // left channel else  DACLRC <= 1'b1; // right chanelend// bufferalways @(posedge BCLK or negedge RST)begin if(!RST)  DACDAT <= 6'b0; else if(CNT_BCLK>=6'd2 && CNT_BCLK<=6'd26)//it's time send left channel    DACDAT <= DATABUF[23]; // shift output else if(CNT_BCLK>=34 && CNT_BCLK<=58) // send right channel  DACDAT <= DATABUF[23]; // shift output else  DACDAT <= 6'b0;end// shift registeralways @(negedge BCLK or negedge RST)begin if(!RST) begin  READ_EN <= 0;  DATABUF <= 24'h0; end else if(CNT_BCLK==6'd0 || CNT_BCLK==6'd32) begin  READ_EN <= 1;  //Read data enable  DATABUF <= DATA_SOURCE; //get data  //DATABUF <= temp; end else if((CNT_BCLK>=6'd2&& CNT_BCLK<=6'd25)||(CNT_BCLK>=6'd34&&CNT_BCLK<=6'd57)) begin  READ_EN <= 0;  DATABUF[23:0] <= {DATABUF[22:0],1'b0}; end else  READ_EN <= 0;end endmodule