赛灵思（Xilinx） FPGA的SRL16移位寄存器原理与使用
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赛灵思（Xilinx） FPGA的SRL16移位寄存器原理与使用
可以定义移位长度的移位寄存器。就是用一个lut可以实现16位的移位寄存器。SRL16 的是 16bit移位寄存器查找表 // 16-Bit Shift Register Look-Up-Table (LUT)在一个LUT中可以实现16个FF移位的功能！SSRL16 SRL16_inst (.Q(Q), // SRL data output.A0(A0), // Select[0] input.A1(A1), // Select[1] input.A2(A2), // Select[2] input.A3(A3), // Select[3] input.CLK(CLK), // Clock input.D(D) // SRL data input);
Xilinx 官网的说明——原理
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SRL16 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted.The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.这里说了几点，- 移位寄存器的初始值可以用INIT属性初始化；- 移位寄存器的长度由地址线的取值决定；- 移位数据从D端输入，Q端输出
- 先移入的数据是MSB
Xilinx 官网的说明——Static Length Mode
To get a fixed length shift register, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula ength = (8*A3) +(4*A2) + (2*A1) + A0 +1
If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones (1111), it is 16 bits long.
Xilinx 官网的说明——Dynamic Length Mode
The length of the shift register can be changed dynamically by changing the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the length of the shift register changes from 16 bits to 8 bits.Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.
Inputs
Output
Am
CLK
D
Q
Am
X
X
Q(Am)
Am
D
Q(Am-1)
m= 0, 1, 2, 3
这里提示了几个要点：- 移位寄存器是可变长度的- 长度的改变由地址线来指定- 内部的寄存器长度是不变的，只是截取的长度变了
- 数据先移入到A0，然后到A1，以此类推，最后从指定长度的Am-1处输出，比如A=8，则数据从地址0输入，从地址7输出，这样有效的移位长度就为8。
Xilinx 官网的说明——VHDL例化实例
- -- SRL16: 16-bit shift register LUT operating on posedge of clock
- -- All FPGAs
- -- Xilinx HDL Libraries Guide version 7.1i
- SRL16_inst : SRL16
- -- The following generic declaration is only necessary if you wish to
- -- change the initial contents of the SRL to anything other than all
- -- zero's.
- generic map (
- INIT => X"0000")
- port map (
- Q => Q, -- SRL data output
- A0 => A0, -- Select[0] input
- A1 => A1, -- Select[1] input
- A2 => A2, -- Select[2] input
- A3 => A3, -- Select[3] input
- CLK => CLK, -- Clock input
- D => D -- SRL data input
- );
- -- End of SRL16_inst instantiation
复制代码
Xilinx 官网的说明——Verilog例化实例
- -- SRL16: 16-bit shift register LUT operating on posedge of clock
- -- All FPGAs
- -- Xilinx HDL Libraries Guide version 7.1i
- SSRL16 SRL16_inst (
- .Q(Q), // SRL data output
- .A0(A0), // Select[0] input
- .A1(A1), // Select[1] input
- .A2(A2), // Select[2] input
- .A3(A3), // Select[3] input
- .CLK(CLK), // Clock input
- .D(D) // SRL data input
- );
- // The following defparam declaration is only necessary if you wish to
- // change the initial contents of the SRL to anything other than all
- // zero's. If the instance name to the SRL is changed, that change
- // needs to be reflected in the defparam statements.
- defparam SRL16_inst.INIT = 16'h0000;
- // End of SRL16_inst instantiation
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