图5 乘法器原语的示意图
在ISE中打开Language-template,verilog— device primitive--- Spartan3--- Arithmetic functions, 就可以看到MULT18*18和MULT18*18S的原语调用代码了。例如MULT18*18的就是
// MULT18X18 : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (MULT18X18_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.
// <-----Cut code below this line---->
// MULT18X18: 18 x 18 signed asynchronous multiplier
// Spartan-3
// Xilinx HDL Language Template, version 12.1
MULT18X18 MULT18X18_inst (
.P(P), // 36-bit multiplier output
.A(A), // 18-bit multiplier input
.B(B) // 18-bit multiplier input
);
// End of MULT18X18_inst instantiation
Xilinx的硬件乘法器很强大,所以心得比较多,要多写几次才能写完了。就在撰写本博文的时候,邮箱里面弹出了Xilinx发来的邮件,7系列的FPGA已经发布了;大概浏览一下,有
Artix-7 FPGA 系列 — 针对最低功耗和最低成本而优化
Kintex-7 FPGA 系列 — 针对更低功耗的经济型信号处理而优化
Virtex-7 FPGA 系列 — 为低功耗和最高系统性能而优化
Spartan系列看来就此消失,被Artix和Kintex来取代了。FPGA的发展速度真是远胜于摩尔定律啊!
附件大小Biao_1_Cheng_Fa_Qi_Yuan_Yu_.jpg34.49 KBTu_1_Spartan6De_Ying_Jian_Cheng_Fa_Qi_.JPG24.46 KBTu_2_Spartan3De_Ying_Jian_Cheng_Fa_Qi_.JPG7.46 KBTu_3_Qian_Ru_Shi_Cheng_Fa_Qi_Shi_Li_.jpg6.27 KBTu_4_3535You_Fu_Hao_Cheng_Fa_Qi_.jpg33.31 KBTu_5_Cheng_Fa_Qi_Yuan_Yu_.jpg13.96 KB