///////////////////////////////////////////////////* Version : V2.0////////////////////////////////////////////////////////#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
/* AHB clock source */
#define RCC_SYSCLK_Div1 ((u32)0x00000000) // AHB 时钟 = 系统时钟 ；
#define RCC_SYSCLK_Div2 ((u32)0x00000080) // AHB 时钟 = 系统时钟/2 ；
#define RCC_SYSCLK_Div4 ((u32)0x00000090) // AHB 时钟 = 系统时钟/4 ；
#define RCC_HCLK_Div4 ((u32)0x00000500) // APBx 时钟 = HCLK/4 ；
/*******************************************************************************
* Function Name : RCC_Configuration
* Description : Configures the different system clocks.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RCC_Configuration(void)
{
RCC_HSICmd(ENABLE);//使能内部高速晶振 ;
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);//选择内部高速时钟作为系统时钟SYSCLOCK=8MHZ
RCC_HCLKConfig(RCC_SYSCLK_Div1);//选择HCLK时钟源为系统时钟SYYSCLOCK
RCC_PCLK1Config(RCC_HCLK_Div4);//APB1时钟为2M
RCC_PCLK2Config(RCC_HCLK_Div4);//APB2时钟为2M
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE);//使能APB2外设GPIOB时钟
}
/*******************************************************************************
* Function Name : RCC_HSICmd
* Description : Enables or disables the Internal High Speed oscillator (HSI).
* HSI can not be stopped if it is used directly or through the
* PLL as system clock.
* Input : - NewState: new state of the HSI.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
* 功能 : 使能或者失能内部高速晶振（HSI）
*******************************************************************************/
void RCC_HSICmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_HSION_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : RCC_SYSCLKConfig
* Description : Configures the system clock (SYSCLK).
* Input : - RCC_SYSCLKSource: specifies the clock source used as system
* clock. This parameter can be one of the following values:
* - RCC_SYSCLKSource_HSI: HSI selected as system clock
* - RCC_SYSCLKSource_HSE: HSE selected as system clock
* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
* Output : None
* Return : None
* 功能 : 设置系统时钟（SYSCLK）；
*******************************************************************************/
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
tmpreg = RCC->CFGR;
/* Clear SW[1:0] bits */
tmpreg &= CFGR_SW_Mask;
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
tmpreg |= RCC_SYSCLKSource;
/* Store the new value */
RCC->CFGR = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_HCLKConfig
* Description : Configures the AHB clock (HCLK).
* Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
* derived from the system clock (SYSCLK).
* This parameter can be one of the following values:
* - RCC_SYSCLK_Div1: AHB clock = SYSCLK
* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
* Output : None
* Return : None
* 功能 : 设置AHB时钟（HCLK）;
*******************************************************************************/
void RCC_HCLKConfig(u32 RCC_SYSCLK)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_HCLK(RCC_SYSCLK));
tmpreg = RCC->CFGR;
/* Clear HPRE[3:0] bits */
tmpreg &= CFGR_HPRE_Reset_Mask;
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
tmpreg |= RCC_SYSCLK;
/* Store the new value */
RCC->CFGR = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_PCLK1Config
* Description : Configures the Low Speed APB clock (PCLK1).
* Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
* derived from the AHB clock (HCLK).
* This parameter can be one of the following values:
* - RCC_HCLK_Div1: APB1 clock = HCLK
* - RCC_HCLK_Div2: APB1 clock = HCLK/2
* - RCC_HCLK_Div4: APB1 clock = HCLK/4
* - RCC_HCLK_Div8: APB1 clock = HCLK/8
* - RCC_HCLK_Div16: APB1 clock = HCLK/16
* Output : None
* Return : None
* 功能 : 设置低速AHB时钟（PCLK1） ；
*******************************************************************************/
void RCC_PCLK1Config(u32 RCC_HCLK)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_RCC_PCLK(RCC_HCLK));
tmpreg = RCC->CFGR;
/* Clear PPRE1[2:0] bits */
tmpreg &= CFGR_PPRE1_Reset_Mask;
/* Set PPRE1[2:0] bits according to RCC_HCLK value */
tmpreg |= RCC_HCLK;
/* Store the new value */
RCC->CFGR = tmpreg;
} |
