/*检测串口数据下降沿*/
reg rx_bit1,rx_bit2,rx_bit3,rx_bit4;
wire neg_rx;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rx_bit1 <= 0;
rx_bit2 <= 0;
rx_bit3 <= 0;
rx_bit4 <= 0;
end
else
begin
rx_bit1 <= rx_bit;
rx_bit2 <= rx_bit1;
rx_bit3 <= rx_bit2;
rx_bit4 <= rx_bit3;
end
end
assign neg_rx = rx_bit4 & rx_bit3 & ~rx_bit2 & ~rx_bit1 ;
reg rx_en; //接收数据高电平使能
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rx_en <= 1'b0;
else if(neg_rx == 1)
rx_en <= 1;
else if(rx_stop ==1)
begin
rx_en <= 0;
end
end
reg rx_stop; //停止标志位
reg [3:0]bit_num; //串口数据位计数
reg [8:0]rx_data_temp; //存储接收到的数据
reg [7:0]rx_data;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rx_data_temp <= 9'b111111111; //初始值设定
bit_num <= 4'b0;
rx_stop <= 0;
end
else if(bit_num == 4'd11)
begin
rx_stop <=1;
bit_num <= 0;
end
else if(bit_data == 1)
begin
bit_num <= bit_num + 1'b1;
case(bit_num)
4'd0: rx_data_temp[0] <= rx_bit; //起始位
4'd1: rx_data_temp[1] <= rx_bit;
4'd2: rx_data_temp[2] <= rx_bit;
4'd3: rx_data_temp[3] <= rx_bit;
4'd4: rx_data_temp[4] <= rx_bit;
4'd5: rx_data_temp[5] <= rx_bit;
4'd6: rx_data_temp[6] <= rx_bit;
4'd7: rx_data_temp[7] <= rx_bit;
4'd8: rx_data_temp[8] <= rx_bit;
default: ;
endcase
end
else
rx_stop <= 0;
rx_data <= rx_data_temp[8:1];
end
endmodule |
