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- UID
- 852722
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// UART TX Logic
Always @ (Posedge Txclk Or Posedge Reset)
If (Reset) Begin
Tx_reg <= 0;
Tx_empty <= 1;
Tx_over_run <= 0;
Tx_out <= 1;
Tx_cnt <= 0;
End Else Begin
If (Ld_tx_data) Begin
If (!Tx_empty) Begin
Tx_over_run <= 0;
End Else Begin
Tx_reg <= Tx_data;
Tx_empty <= 0;
End
End
If (Tx_enable && !Tx_empty) Begin
Tx_cnt <= Tx_cnt + 1;
If (Tx_cnt == 0) Begin
Tx_out <= 0;
End
If (Tx_cnt > 0 && Tx_cnt < 9) Begin
Tx_out <= Tx_reg[Tx_cnt -1];
End
If (Tx_cnt == 9) Begin
Tx_out <= 1;
Tx_cnt <= 0;
Tx_empty <= 1;
End
End
If (!Tx_enable) Begin
Tx_cnt <= 0;
End
End
Endmodule |
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