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- UID
- 852722
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Function To_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) Return UNSIGNED Is
Variable Result: UNSIGNED(SIZE-1 Downto 0);
Variable Temp: Integer;
Attribute SYNTHESIS_RETURN Of Result:variable Is "FEED_THROUGH" ;
Begin
Temp := ARG;
For I In 0 To SIZE-1 Loop
If (Temp Mod 2) = 1 Then
Result(I) := ''1'';
Else
Result(I) := ''0'';
End If;
If Temp > 0 Then
Temp := Temp / 2;
Else
Temp := (Temp - 1) / 2;
End If;
End Loop;
Return Result;
End;
Constant Zero : UNSIGNED(Data_width Downto 1) := (Others => ''0'') ;
Begin
PRIO : Process(Data)
Variable Temp_address : UNSIGNED(Address_width - 1 Downto 0) ;
Begin
Temp_address := (Others => ''0'') ;
For I In Data_width - 1 Downto 0 Loop
If (Data(I) = ''1'') Then
Temp_address := To_unsigned(I,Address_width) ;
Exit ;
End If ;
End Loop ;
Address <= Temp_address ;
None <= To_stdlogic(Data = Zero) ;
End Process ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Use IEEE.Std_logic_unsigned.All ;
Entity Ram Is
Generic (Data_width : Natural := 8 ;
Address_width : Natural := 8);
Port (
Data_in : In UNSIGNED(Data_width - 1 Downto 0) ;
Address : In UNSIGNED(Address_width - 1 Downto 0) ;
We : In Std_logic ;
Clk : In Std_logic;
Data_out : Out UNSIGNED(Data_width - 1 Downto 0)
);
End Ram ;
Architecture Rtl Of Ram Is
Type Mem_type Is Array (2**Address_width Downto 0) Of UNSIGNED(Data_width - 1 Downto 0) ;
Signal Mem : Mem_type ;
Signal Addr_reg : Unsigned (Address_width -1 Downto 0);
Begin
Data_out <= Mem(Conv_integer(Addr_reg)) ;
I0 : Process
Begin
Wait Until Clk''Event And Clk = ''1'';
If (We = ''1'') Then
Mem(Conv_integer(Address)) <= Data_in ;
End If ;
Addr_reg <= Address;
End Process ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Tbuf Is
Generic (Data_width : Natural := 16 );
Port (
Data_in : In UNSIGNED(Data_width - 1 Downto 0) ;
En : In Std_logic ;
Data_out : Out UNSIGNED(Data_width - 1 Downto 0)
);
End Tbuf ; |
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