Architecture Rtl Of Tbuf Is
Begin
Three_state : Process(Data_in,En)
Begin
If (En = ''1'') Then
Data_out <= Data_in ;
Else
Data_out <= (Others => ''Z'') ;
End If;
End Process ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Pseudorandom Is
Generic (Data_width : Natural := 8 );
Port (
Seed : In UNSIGNED (24 Downto 0) ;
Init : In UNSIGNED (4 Downto 0) ;
Load : In Std_logic ;
Clk : In Std_logic ;
Reset : In Std_logic ;
Read : In Std_logic ;
Write : In Std_logic ;
Rand : Out UNSIGNED (7 Downto 0) ;
None : Out Std_logic
);
End Pseudorandom ;
Architecture Rtl Of Pseudorandom Is
Signal Latch_seed : UNSIGNED(24 Downto 0) ;
Signal Encoder_address : UNSIGNED(4 Downto 0) ;
Signal Random_data : UNSIGNED(7 Downto 0) ;
Signal Write_enable : Std_logic ;
Signal Ram_data : UNSIGNED(7 Downto 0) ;
Begin
I0 : Entity Work.Dlatrg(Rtl)
Generic Map (25)
Port Map (Seed,Read,Reset,Latch_seed) ;
I1 : Entity Work.Priority_encoder(Rtl)
Generic Map (25,5)
Port Map (Latch_seed,Encoder_address,None) ;
I2 : Entity Work.Ram(Rtl)
Generic Map (8,5)
Port Map (Random_data,Encoder_address,Write_enable,Clk,Ram_data) ;
I3 : Entity Work.Tbuf(Rtl)
Generic Map (8)
Port Map (Ram_data,Write,Rand) ;
I4 : Entity Work.Lfsr(Rtl)
Generic Map (8)
Port Map (Clk,Reset,Random_data) ;
I5 : Entity Work.Divide_by_n(Rtl)
Generic Map (5)
Port Map (Init,Load,Clk,Reset,Write_enable) ;
End Rtl ;
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