static int write_byte(uint32_t addr, uint8_t byte)
{
uint32_t word, var, val;
var = byte;
writel(var, (void *)(spi_char.mem_virt+SPI_DATA0));
writel(addr, (void*)(spi_char.mem_virt+SPI_ADDR));
word = readw((void *)(spi_char.mem_virt+SPI_CTRL));
word |= SPI_CTRL_SCGO; /* set cycle */
word |= SPI_CTRL_ACS; /* Enable Atomic Cycle Sequence */
word &= ~SPI_CTRL_SPOP;
word &= ~SPI_CTRL_COP;
word = word | SPI_CTRL_OPMENU_WR<<SPI_CTRL_COP_SHIFT; /* write */
word &= ~SPI_CTRL_DBC;
word = word | 0x00<<SPI_CTRL_DBC_SHIFT; /* write count=1 */
word |= SPI_CTRL_DC;
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
writew(word, (void *)(spi_char.mem_virt+SPI_CTRL));
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
word = readw((void *)(spi_char.mem_virt+SPI_STATUS));
word |= SPI_STATUS_CDS; /* clear Cycle Done Status flag */
word |= SPI_STATUS_BAS; /* clear blocked flag */
writew(word, (void *)(spi_char.mem_virt+SPI_STATUS));
return (1);
}
static uint8_t read_byte(uint32_t addr)
{
uint32_t word, var, val;
uint8_t ret;
word = readw((void *)(spi_char.mem_virt+SPI_STATUS));
word |= SPI_STATUS_CDS; /* clear Cycle Done Status flag */
word |= SPI_STATUS_BAS; /* clear blocked flag */
writew(word, (void *)(spi_char.mem_virt+SPI_STATUS));
writel(addr, (void*)(spi_char.mem_virt+SPI_ADDR));
word = readw((void *)(spi_char.mem_virt+SPI_CTRL));
word |= SPI_CTRL_SCGO; /* set cycle */
word &= ~SPI_CTRL_ACS; /* Diable Atomic Cycle Sequence */
//word &= ~SPI_CTRL_SPOP;
word &= ~SPI_CTRL_COP;
word = word | SPI_CTRL_OPMENU_RD<<SPI_CTRL_COP_SHIFT; /* read */
word &= ~SPI_CTRL_DBC;
word = word | 0x00<<SPI_CTRL_DBC_SHIFT; /* read count=1 */
word |= SPI_CTRL_DC;
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
writew(word, (void *)(spi_char.mem_virt+SPI_CTRL));
SPI_DBG("read_byte: ctrl=%08x/n", word);
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
var = readl((void *)(spi_char.mem_virt+SPI_DATA0));
SPI_DBG("read_byte: data=%08x", var);
ret = var & 0xFF;
word = readw((void *)(spi_char.mem_virt+SPI_STATUS));
word |= SPI_STATUS_CDS; /* clear Cycle Done Status flag */
word |= SPI_STATUS_BAS; /* clear blocked flag */
writew(word, (void *)(spi_char.mem_virt+SPI_STATUS));
return (ret);
}
static int erase_chip(void)
{
uint32_t word, var, val;
/* disable flash protection */
if(is_flash_protection())
{
if(!disable_flash_protection())
{
SPI_ERR("can't disable flash protection/n");
return (0);
}
SPI_DBG("erase_chip is_flash_protection/n") ;
}
word = readw((void *)(spi_char.mem_virt+SPI_CTRL));
word |= SPI_CTRL_SCGO; /* set cycle */
word |= SPI_CTRL_ACS; /* Enable Atomic Cycle Sequence */
word &= ~SPI_CTRL_SPOP;
word &= ~SPI_CTRL_COP;
word = word | SPI_CTRL_OPMENU_CHIPERASE<<SPI_CTRL_COP_SHIFT; /* write */
word &= ~SPI_CTRL_DBC;
word = word | 0x00<<SPI_CTRL_DBC_SHIFT; /* write count=1 */
word &= ~SPI_CTRL_DC;
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
writew(word, (void *)(spi_char.mem_virt+SPI_CTRL));
/* check the status */
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));
while(val & SPI_STATUS_SCIP)
{
val = readw((void *)(spi_char.mem_virt+SPI_STATUS));/* check the status */
}
word = readw((void *)(spi_char.mem_virt+SPI_STATUS));
word |= SPI_STATUS_CDS; /* clear Cycle Done Status flag */
word |= SPI_STATUS_BAS; /* clear blocked flag */
writew(word, (void *)(spi_char.mem_virt+SPI_STATUS));
SPI_DBG("erase_chip() end/n");
return (1);
} |