7系列FPGA中有关IOSTANDARD警告和错误的处理方法 undefined, specific, design, 比特流, ERROR

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因为新版本的ISE和Vivado软件中对管脚约束进行了增强限制，所以有关IOSTANDARD的警告和错误是为了避免把一个电压水平的管脚误放到另一种电平上，导致意外损坏芯片。这个检查很有用，但是对于习惯使用默认设置的人会造成一些困惑，例如在ISE中布局布线时会提示警告：PAD symbol "XXXX" has an undefined IOSTANDARD在此警告出现之后，就基本已经无法正常生成比特流了， 会提示警告：ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"在Vivado中则会提示的更清楚一些： [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 50 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: feedback_current[15:0], ref_current[15:0], voltage_out[15:0], clock, reset. 说明了我们使用了默认值，而安全起见是需要用户自定义电平标准的。软件给出了一些脚本的更改方法，不过也挺麻烦的，简单尝试了一下，ISE开发时直接在ucf里面限制就好了，例如：把NET "reset"  LOC= P20;改成NET "reset" IOSTANDARD = LVCMOS18 | LOC= P20;就可以了。其实PlanAhead里面P20管脚的默认电平本来就是LVCMOS18了，为了器件安全我们只好加这么一步了。Vivado开发的话则是修改xdc文件：set_property IOSTANDARD LVCMOS18 [get_ports {voltage_out[15]}]