`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company:// Engineer://// Create Date: 17:01:38 10/09/06// Design Name: // Module Name: ppeifir// Project Name: // Target Device: // Tool versions: // Description:用Verilog编写的fir滤波器程序//// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments://////////////////////////////////////////////////////////////////////////////////module firv2(clk, x, y); input clk; input [7:0] x; output [25:0] y; reg [26:0] y;
reg[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16; wire[21:0] acc1,acc2,acc3,acc4,acc5,acc6,acc7,acc8,acc9,acc10,acc11,acc12,acc13,acc14,acc15,acc16,acc17;
reg [8:0]sxin[0:32]; reg [5:0]i,k; reg [8:0]xx[16:0]; parameter c0=-21, c1=-8, c2= 22, c3=34, c4=6, c5=-34, c6=-31, c7=32, c8=87, c9=32, c10=-154, c11=-321, c12=-217, c13=321, c14=1185, c15=1996, c16=2328;
always @ (posedge clk) begin xx[16]<=sxin[16] ; for(i=0;i<16;i=i+1) xx<=sxin+sxin[32-i] ; for(k=32;k>0;k=k-1) sxin[k]<=sxin[k-1]; sxin[0]<={x[7],x};
end
mult13_8 uut0(clk,c0,xx[0],acc1);mult13_8 uut1(clk,c1,xx[1],acc2);mult13_8 uut2(clk,c2,xx[2],acc3);mult13_8 uut3(clk,c3,xx[3],acc4);mult13_8 uut4(clk,c4,xx[4],acc5);mult13_8 uut5(clk,c5,xx[5],acc6);mult13_8 uut6(clk,c6,xx[6],acc7);mult13_8 uut7(clk,c7,xx[7],acc8);mult13_8 uut8(clk,c8,xx[8],acc9);mult13_8 uut9(clk,c9,xx[9],acc10);mult13_8 uut10(clk,c10,xx[10],acc11);mult13_8 uut11(clk,c11,xx[11],acc12);mult13_8 uut12(clk,c12,xx[12],acc13);mult13_8 uut13(clk,c13,xx[13],acc14);mult13_8 uut14(clk,c14,xx[14],acc15); mult13_8 uut15(clk,c15,xx[15],acc16); mult13_8 uut16(clk,c16,xx[16],acc17);
always @(posedge clk) begin y<={acc16[1],acc16[1],acc16[1],acc16[1],acc16[1],acc16}+{acc17[1],acc17[1],acc17[1],acc17[1],acc17[1],acc17} +{acc15[1],acc15[1],acc15[1],acc15[1],acc15[1],acc15}+{acc14[1],acc14[1],acc14[1],acc14[1],acc14[1],acc14} +{acc13[1],acc13[1],acc13[1],acc13[1],acc13[1],acc13}+{acc12[1],acc12[1],acc12[1],acc12[1],acc12[1],acc12} +{acc11[1],acc11[1],acc11[1],acc11[1],acc11[1],acc11}+{acc10[1],acc10[1],acc10[1],acc10[1],acc10[1],acc10} +{acc9[1],acc9[1],acc9[1],acc9[1],acc9[1],acc9}+{acc8[1],acc8[1],acc8[1],acc8[1],acc8[1],acc8} +{acc7[1],acc7[1],acc7[1],acc7[1],acc7[1],acc7}+{acc6[1],acc6[1],acc6[1],acc6[1],acc6[1],acc6} +{acc5[1],acc5[1],acc5[1],acc5[1],acc5[1],acc5}+{acc4[1],acc4[1],acc4[1],acc4[1],acc4[1],acc4} +{acc3[1],acc3[1],acc3[1],acc3[1],acc3[1],acc3}+{acc2[1],acc2[1],acc2[1],acc2[1],acc2[1],acc2} +{acc1[1],acc1[1],acc1[1],acc1[1],acc1[1],acc1}; end
endmodule |
