Xilinx定义了如下几种约束类型：
• “Attributes and Constraints”
• “CPLD Fitter”
• “Grouping Constraints”
• “Logical Constraints”
• “Physical Constraints”
• “Mapping Directives”
• “Placement Constraints”
• “Routing Directives”
• “Synthesis Constraints”
• “Timing Constraints”
• “Configuration Constraints”
通过编译UCF（user constraints file）文件可以完成上述的功能。
还是用实例来讲UCF的语法是如何的。
[img]https://6eyzew.bay.livefilestore.com/y1mq_D8bB5bsJplIkEA2AYFduxmN-ilLAaS4j6XdoBY1Vl0X369zo9oiGTcOEDv_uggTemsfcm8miKSOT-xoUj59e9Z8W3iiRBvo7wKi_FgJ0r7Q6tK3z1g12rlZSnD6eouIwoqrkzWwv535fGx7anh1g/image_thumb[1]%200F490D17.png[/img]
图1 RTL Schematic
图1 是顶层文件RTL图，左侧一列输入，右侧为输出，这些端口需要分配相应的FPGA管脚。
1: NET "pin_sysclk_i" LOC = AD12 | TNM_NET = pin_sysclk_i; 2: TIMESPEC TS_pin_sysclk_i = PERIOD "pin_sysclk_i" 15 ns HIGH 50 %; 3: # 4: NET "pin_plx_lreset_n_i" LOC = B18; 5: # 6: NET "pin_plx_lhold_i" LOC = C17; 7: NET "pin_plx_lholda_o" LOC = D17 | SLEW = FAST; 8: # 9: NET "pin_plx_ads_n_i" LOC = E18; 10: NET "pin_plx_ads_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH; 11: # 12: NET "pin_plx_lw_r_n_i" LOC = E9; 13: NET "pin_plx_lw_r_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH; 14: # 15: NET "pin_plx_blast_n_i" LOC = D18; 16: NET "pin_plx_blast_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH; 17: # 18: NET "pin_plx_lad_io<0>" LOC = AD13 | SLEW = FAST | TNM = LAD; 19: NET "pin_plx_lad_io<1>" LOC = AC13 | SLEW = FAST | TNM = LAD; 20: NET "pin_plx_lad_io<2>" LOC = AC15 | SLEW = FAST | TNM = LAD; 21: NET "pin_plx_lad_io<3>" LOC = AC16 | SLEW = FAST | TNM = LAD; 22: NET "pin_plx_lad_io<4>" LOC = AA11 | SLEW = FAST | TNM = LAD; 23: NET "pin_plx_lad_io<5>" LOC = AA12 | SLEW = FAST | TNM = LAD; 24: NET "pin_plx_lad_io<6>" LOC = AD14 | SLEW = FAST | TNM = LAD; 25: NET "pin_plx_lad_io<7>" LOC = AC14 | SLEW = FAST | TNM = LAD; 26: NET "pin_plx_lad_io<8>" LOC = AA13 | SLEW = FAST | TNM = LAD; 27: NET "pin_plx_lad_io<9>" LOC = AB13 | SLEW = FAST | TNM = LAD; 28: NET "pin_plx_lad_io<10>" LOC = AA15 | SLEW = FAST | TNM = LAD; 29: NET "pin_plx_lad_io<11>" LOC = AA16 | SLEW = FAST | TNM = LAD; 30: NET "pin_plx_lad_io<12>" LOC = AC11 | SLEW = FAST | TNM = LAD; 31: NET "pin_plx_lad_io<13>" LOC = AC12 | SLEW = FAST | TNM = LAD; 32: NET "pin_plx_lad_io<14>" LOC = AB14 | SLEW = FAST | TNM = LAD; 33: NET "pin_plx_lad_io<15>" LOC = AA14 | SLEW = FAST | TNM = LAD; 34: NET "pin_plx_lad_io<16>" LOC = D12 | SLEW = FAST | TNM = LAD; 35: NET "pin_plx_lad_io<17>" LOC = E13 | SLEW = FAST | TNM = LAD; 36: NET "pin_plx_lad_io<18>" LOC = C16 | SLEW = FAST | TNM = LAD; 37: NET "pin_plx_lad_io<19>" LOC = D16 | SLEW = FAST | TNM = LAD; 38: NET "pin_plx_lad_io<20>" LOC = D11 | SLEW = FAST | TNM = LAD; 39: NET "pin_plx_lad_io<21>" LOC = C11 | SLEW = FAST | TNM = LAD; 40: NET "pin_plx_lad_io<22>" LOC = E14 | SLEW = FAST | TNM = LAD; 41: NET "pin_plx_lad_io<23>" LOC = D15 | SLEW = FAST | TNM = LAD; 42: NET "pin_plx_lad_io<24>" LOC = D13 | SLEW = FAST | TNM = LAD; 43: NET "pin_plx_lad_io<25>" LOC = D14 | SLEW = FAST | TNM = LAD; 44: NET "pin_plx_lad_io<26>" LOC = F15 | SLEW = FAST | TNM = LAD; 45: NET "pin_plx_lad_io<27>" LOC = F16 | SLEW = FAST | TNM = LAD; 46: NET "pin_plx_lad_io<28>" LOC = F11 | SLEW = FAST | TNM = LAD; 47: NET "pin_plx_lad_io<29>" LOC = F12 | SLEW = FAST | TNM = LAD; 48: NET "pin_plx_lad_io<30>" LOC = F13 | SLEW = FAST | TNM = LAD; 49: NET "pin_plx_lad_io<31>" LOC = F14 | SLEW = FAST | TNM = LAD; 50: TIMEGRP "LAD" OFFSET = IN 6.4 ns AFTER "pin_sysclk_i" HIGH; 51: TIMEGRP "LAD" OFFSET = OUT 3.1 ns BEFORE "pin_sysclk_i" HIGH; 52: # 53: NET "pin_plx_ready_n_o" LOC = F18 | SLEW = FAST; 54: NET "pin_plx_ready_n_o" OFFSET = OUT 4.2 ns BEFORE "pin_sysclk_i" HIGH; 55: # 56: NET "pin_plx_bterm_n_o" LOC = D10 | SLEW = FAST; 57: NET "pin_plx_bterm_n_o" OFFSET = OUT 4.2 ns BEFORE "pin_sysclk_i" HIGH; 58: # 59: NET "pin_led_o<0>" LOC = D22; 60: NET "pin_led_o<1>" LOC = C22; 61: NET "pin_led_o<2>" LOC = E21; 62: NET "pin_led_o<3>" LOC = D21; 63: NET "pin_led_o<4>" LOC = C21; 64: NET "pin_led_o<5>" LOC = B24; 65: NET "pin_led_o<6>" LOC = C20; 66: NET "pin_led_o<7>" LOC = B23;
表1. UCF example
对上面的UCF文件进行一些注释：
该UCF文件主要是完成了管脚的约束、时钟的约束，以及组的约束。
第一、二行：主要定义了时钟以及对应的物理管脚。
第一行，端口pin_sysclk_i 分配到FPGA管脚AD12，并放到了 pin_sysclk_i group中。那如何得知是AD12的管脚呢，请看图2，FPGA管脚AD12 是一个66MHz的外部时钟。FPGA的开发板肯定有电路原理图供你分配外部管脚。
[img]https://6eyzew.bay.livefilestore.com/y1mTaNaqy3dBKJoKeVAJHP4FeLJZd_RntlYpUuEuDE1oMfyi2oxhDD3Q-RR8PvS6uoh2zTPNDNGnFof2Umnv3xBuAlSAVZI5bIjgN6m8y_Y4T5tacBeFd8qDf5bfMgpCMtRuKQwCv18QhYU2_MZKwkgdQ/image_thumb[3]%205EE3BBD0.png[/img]
图2，电路原理图
第二行：时钟说明：周期15ns，占空比50%。关键词TIMESPEC（Timing Specifications），即时钟说明。一般的语法是：
TIMESPEC
"TSidentifier"=PERIOD
"timegroup_name" value [units];
其中TSidentifier用来指定TS（时钟说明）的唯一的名称。
第七行：pin_plx_lholda_o 连接至物理管脚 D17，并配置该管脚电平变化的速率。关键词：SLEW，用来定义电平变化的速率的，一般语法是：
NET
"top_level_port_name"
SLEW="value";
其中value = {FAST|SLOW|QUIETIO}, QUIETIO仅用在Spartan-3A。
第十行：定义pin_plx_ads_n_i 输入跟时钟的关系。OFFSET IN和OFFSET OUT的约束。OFFSET IN 定义了数据输入的时间和接收数据时钟沿（capture Edge）的关系。 | 
