Xilinx Spartan6 LX150T开发方案 连接器, 收发器, 以太网, 开发, 比特

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　　Avnet公司的Xilinx Spartan-6 LX150T开发套件是采用Xilinx公司的XC6SLX150T-3FGG676器件，它的串行吉比特收发器接口（GTP）能连接到片上PCI Express® x1硬宏元或PCI Express x4软宏元，一个SFP连接器和一个SATA主接口。系统板包括DDR3，SDRAM，闪存，10/100/1000以太网PHY和串行口，其它特性还包括USB端口。
        　　可编LVDS时钟，用户开关和LED，还提供两个FMC LPC扩展槽和总数136个高速单端和差分用户I/O.本文介绍了Xilinx Spartan-6 FPGA主要特性和系列产品，几种应用框图以及Xilinx Spartan-6 LX150T开发板主要特性，框图，电路图和材料清单。
        　　Spartan®-6 LX FPGAs are optimized for applications that require the absolute lowest cost. Now with up to 42% less power consumption and a 12% increase in performance enabled by ISE® Design Suite， they provide up to 150K logic cells， integrated PCI Express® blocks， advanced memory support， 250MHz DSP slices， and 3.2Gbps low-power transceivers.
        　　Spartan 6 LX150T Development Board
        　　The Spartan-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3，840 to 147，443 logic cells， with half the power consumption of previous Spartan families， and faster， more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost， power， and performance， the Spartan-6 family offers a new， more efficient， dual-register 6-input lookup table （LUT） logic and a rich selection of built-in system-level blocks. These include 18 Kb （2 x 9 Kb） block RAMs， second generation DSP48A1 slices， SDRAM memory controllers， enhanced mixed-mode clock management blocks， SelectIO？technology， poweroptimized high-speed serial transceiver blocks， PCI Express？compatible Endpoint blocks， advanced system-level power management modes， auto-detect configuration options， and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs， consumer-oriented DSP designs， and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.
        　　Spartan-6 FPGA主要特性：
        　　Spartan-6 Family：
        　　Spartan-6 LX FPGA： Logic optimized
        　　Spartan-6 LXT FPGA： High-speed serial connectivity
        　　Designed for low cost
        　　Multiple efficient integrated blocks
        　　Optimized selection of I/O standards
        　　Staggered pads
        　　High-volume plastic wire-bonded packages
        　　Low static and dynamic power
        　　45 nm process optimized for cost and low power
        　　Hibernate power-down mode for zero power
        　　Suspend mode maintains state and configuration with multi-pin wake-up， control enhancement
        　　Lower-power 1.0V core voltage （LX FPGAs， -1L only）
        　　High performance 1.2V core voltage （LX and LXT
        　　FPGAs， -2， -3， and -3N speed grades）
        　　Multi-voltage， multi-standard SelectIO？interface banks
        　　Up to 1，080 Mb/s data transfer rate per differential I/O
        　　Selectable output drive， up to 24 mA per pin
        　　3.3V to 1.2V I/O standards and protocols
        　　Low-cost HSTL and SSTL memory interfaces
        　　Hot swap compliance
        　　Adjustable I/O slew rates to improve signal integrity
        　　High-speed GTP serial transceivers in the LXT FPGAs
        　　Up to 3.2 Gb/s
        　　High-speed interfaces including： Serial ATA， Aurora，
        　　1G Ethernet， PCI Express， OBSAI， CPRI， EPON， GPON， DisplayPort， and XAUI
        　　Integrated Endpoint block for PCI Express designs （LXT）
        　　Low-cost PCI？technology support compatible with the
        　　33 MHz， 32- and 64-bit specification.
        　　Efficient DSP48A1 slices
        　　High-performance arithmetic and signal processing
        　　Fast 18 x 18 multiplier and 48-bit accumulator
        　　Pipelining and cascading capability
        　　Pre-adder to assist filter applications
        　　Integrated Memory Controller blocks
        　　DDR， DDR2， DDR3， and LPDDR support
        　　Data rates up to 800 Mb/s （12.8 Gb/s peak bandwidth）
        　　Multi-port bus structure with independent FIFO to reduce design timing issues
        　　Abundant logic resources with increased logic capacity
        　　Optional shift register or distributed RAM support
        　　Efficient 6-input LUTs improve performance and minimize power
        　　LUT with dual flip-flops for pipeline centric applications
        　　Block RAM with a wide range of granularity
        　　Fast block RAM with byte write enable
        　　18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs
        　　Clock Management Tile （CMT） for enhanced performance
        　　Low noise， flexible clocking
        　　Digital Clock Managers （DCMs） eliminate clock skew and duty cycle distortion
        　　Phase-Locked Loops （PLLs） for low-jitter clocking
        　　Frequency synthesis with simultaneous multiplication， division， and phase shifting
        　　Sixteen low-skew global clock networks
        　　Simplified configuration， supports low-cost standards
        　　2-pin auto-detect configuration
        　　Broad third-party SPI （up to x4） and NOR flash support
        　　Feature rich Xilinx Platform Flash with JTAG