SystemVerilog给予Verilog、VHDL和C/C++优点为一身的硬件描述语言，很值得学一学。
1、8-bit up counter
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module up_counter(
output reg [7:0] out , // Output of the counter
input wire enable , // enable for counter
input wire clk , // clock Input
input wire reset // reset Input
);
//-------------Code Starts Here-------
always_ff @(posedge clk)
if (reset) out <= 8'b0 ;
else if (enable) out ++;
endmodule
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2、8-bit up counter with load
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module up_counter_load (
output reg [7:0] out , // Output of the counter
input wire [7:0] data , // Parallel load for the counter
input wire load , // Parallel load enable
input wire enable , // Enable counting
input wire clk , // clock input
input wire reset // reset input
);
//-------------Code Starts Here-------
always_ff @ (posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (load) begin
out <= data;
end else if (enable) begin
out++;
end
endmodule
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3、8-bit up-down counter
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module up_down_counter (
output reg [7:0] out , // Output of the counter
input wire up_down , // up_down control for counter
input wire clk , // clock input
input wire reset // reset input
);
//-------------Code Starts Here-------
always_ff @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out ++;
end else begin
out --;
end
endmodule
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4、lfsr counter
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module lfsr (
output reg [7:0] out , // Output of the counter
input wire enable , // Enable for counter
input wire clk , // clock input
input wire reset // reset input
);
//------------Internal Variables--------
wire linear_feedback;
//-------------Code Starts Here-------
assign linear_feedback = !(out[7] ^ out[3]);
always_ff @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (enable) begin
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule // End Of Module counter
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