Excuse me for asking in English, but I don't know Chinese I'm a developer from Belarus, and I'm trying to develop my first project in VHDL for CPLD. The project is simple but resource-expensive (i.e. it contains two 168-bit registers and a couple of 8-, 7-, 6- and 5-bit). When I'm trying to fit it into Xilinx CPLD with 512 macrocells, it does fit without any problems, but Quartus II 4.1 (with free web license) doesn't fit it into appropriate Altera's CPLD even when I shorten my long registers: it cannot place my outputs (I have 3 8-bit outputs and 1 16-bit) after more than 3 minutes of thinking. I don't think that Altera's and Xilinx's CPLDs differ too much internally, so I think this is something with Quartus. What do you think about this?
