附2:AXI4的测试模块与仿真测试`timescale 1ns/1nsmodule conv_axi_test(); parameter integer C_S00_AXI_DATA_WIDTH = 32; parameter integer C_S00_AXI_ADDR_WIDTH = 6; reg s00_axi_aclk; // 全局复位信号 reg s00_axi_aresetn; reg [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr; wire [2 : 0] s00_axi_awprot; reg s00_axi_awvalid; wire s00_axi_awready; reg [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata; reg [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb; reg s00_axi_wvalid; wire s00_axi_wready; wire [1 : 0] s00_axi_bresp; wire s00_axi_bvalid; wire s00_axi_bready; reg [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr; wire [2 : 0] s00_axi_arprot; reg s00_axi_arvalid; wire s00_axi_arready; wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata; wire [1 : 0] s00_axi_rresp; wire s00_axi_rvalid; wire s00_axi_rready; conv_v1_0_S00_AXI # ( .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) ) conv_v1_0_S00_AXI_inst ( .S_AXI_ACLK(s00_axi_aclk), .S_AXI_ARESETN(s00_axi_aresetn), .S_AXI_AWADDR(s00_axi_awaddr), .S_AXI_AWPROT(s00_axi_awprot), .S_AXI_AWVALID(s00_axi_awvalid), .S_AXI_AWREADY(s00_axi_awready), .S_AXI_WDATA(s00_axi_wdata), .S_AXI_WSTRB(s00_axi_wstrb), .S_AXI_WVALID(s00_axi_wvalid), .S_AXI_WREADY(s00_axi_wready), .S_AXI_BRESP(s00_axi_bresp), .S_AXI_BVALID(s00_axi_bvalid), .S_AXI_BREADY(s00_axi_bready), .S_AXI_ARADDR(s00_axi_araddr), .S_AXI_ARPROT(s00_axi_arprot), .S_AXI_ARVALID(s00_axi_arvalid), .S_AXI_ARREADY(s00_axi_arready), .S_AXI_RDATA(s00_axi_rdata), .S_AXI_RRESP(s00_axi_rresp), .S_AXI_RVALID(s00_axi_rvalid), .S_AXI_RREADY(s00_axi_rready) );initialbegin:d integer i; s00_axi_aclk = 1; for(i = 0; i< 1000;i++) begin #1 s00_axi_aclk = ~ s00_axi_aclk; end $finish();endinitialbegin s00_axi_aresetn = 0; s00_axi_arvalid = 0;#4 s00_axi_aresetn = 1; s00_axi_awvalid = 1; s00_axi_wvalid = 1; s00_axi_awaddr = 0; s00_axi_wstrb = 4'b1111; s00_axi_wdata = 3;#4 s00_axi_awaddr = 6'b000100; s00_axi_wdata = 21;#4 s00_axi_awaddr = 6'b001000; s00_axi_wdata = 19;#4 s00_axi_awaddr = 6'b001100; s00_axi_wdata = 22;#4 s00_axi_awaddr = 6'b010000; s00_axi_wdata = 20;#4 s00_axi_awaddr = 6'b010100; s00_axi_wdata = 13;#4 s00_axi_awaddr = 6'b011000; s00_axi_wdata = 16;#4 s00_axi_awaddr = 6'b011100; s00_axi_wdata = 14;#4 s00_axi_awaddr = 6'b100000; s00_axi_wdata = 7;#4 s00_axi_arvalid = 1; s00_axi_araddr = 6'b100100;endinitialbegin $dumpfile("test.vcd"); $dumpvars();endendmodule利用iverilog进行仿真GTKwave显示测试波形如下
新建IP核如下:
工程顶层图如下:
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