数字电路设计之五级流水线设计（CPU）仿真

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look_w发表于 2017-11-4 12:39 | 只看该作者

数字电路设计之五级流水线设计（CPU）仿真

本帖最后由 look_w 于 2017-11-4 12:50 编辑

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:53:17 10/25/2013
// Design Name: CPU
// Module Name: F:/Digital_Practice/Practice/CPU/stimulus2.v
// Project Name: CPU
// Revision 0.01 - File Created
////////////////////////////////////////////////////////////////////////////////
// state macro define
`define idle 1'b0
`define exec 1'b1
// instruction macro define
`define NOP 5'b00000
`define HALT 5'b00001
`define LOAD 5'b00010
`define STORE 5'b00011
`define SLL 5'b00100
`define SLA 5'b00101
`define SRL 5'b00110
`define SRA 5'b00111
`define ADD 5'b01000
`define ADDI 5'b01001
`define SUB 5'b01010
`define SUBI 5'b01011
`define CMP 5'b01100
`define AND 5'b01101
`define OR 5'b01110
`define XOR 5'b01111
`define LDIH 5'b10000
`define ADDC 5'b10001
`define SUBC 5'b10010
`define JUMP 5'b11000
`define JMPR 5'b11001
`define BZ 5'b11010
`define BNZ 5'b11011
`define BN 5'b11100
`define BNN 5'b11101
`define BC 5'b11110
`define BNC 5'b11111
// general register
`define gr0 3'b000
`define gr1 3'b001
`define gr2 3'b010
`define gr3 3'b011
`define gr4 3'b100
`define gr5 3'b101
`define gr6 3'b110
`define gr7 3'b111
module stimulus2;
// Inputs
reg reset;
reg enable;
reg start;
reg clock;
reg [15:0] i_datain;
reg [15:0] d_datain;
// Outputs
wire d_we;
wire [7:0] i_addr;
wire [7:0] d_addr;
wire [15:0] d_dataout;
// Instantiate the Unit Under Test (UUT)
CPU uut (
.reset(reset),
.enable(enable),
.start(start),
.clock(clock),
.i_datain(i_datain),
.d_datain(d_datain),
.d_we(d_we),
.i_addr(i_addr),
.d_addr(d_addr),
.d_dataout(d_dataout)
);
initial begin
$dumpfile("CPU.vcd");
$dumpvars(1,stimulus2.uut);
// Initialize Inputs
clock = 0;
reset = 0;
start = 0;
enable = 0;
d_datain = 0;
i_datain = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
//************* test pattern *************//
$display("LOAD,ADD,HALT,SUB,STORE");
$display("pc: id_ir :reg_A:reg_B:ALUo:reg_C:da:dd :w:reC1:gr1 :gr2 :gr3 :exir:mmir:wbir:smdr");
$monitor("%h:%b:%h :%h :%h :%h :%h:%h:%b:%h:%h:%h:%h:%h:%h:%h:%h:%b",
uut.pc, uut.id_ir, uut.reg_A, uut.reg_B, uut.ALUo,uut.reg_C,
d_addr, d_dataout, d_we, uut.reg_C1, uut.gr[1], uut.gr[2], uut.gr[3],uut.ex_ir,uut.mem_ir,uut.wb_ir,uut.smdr,uut.zf);
enable <= 1; start <= 0; i_datain <= 0; d_datain <= 0; /*select_y <= 0;*/
#10 reset <= 0;
#10 reset <= 1;
#10 enable <= 1;
#10 start <= 1;
#10 start <= 0;
i_datain <= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
d_datain <= 16'hfC00; // 3 clk later from LOAD
#10 i_datain <= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
#10;//阻塞相当于延迟一个周期取i_datain
#10 i_datain <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
#10 i_datain <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
d_datain <= 16'h10AB;
#10 i_datain <= {`ADDC, `gr3, 1'b0, `gr2, 1'b0, `gr1};
#10 i_datain <= {`SUB, `gr3, 1'b0, `gr2, 1'b0, `gr1};
#10 i_datain <= {`SUBC, `gr3, 1'b0, `gr2, 1'b0, `gr1};
#10 i_datain <= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
//#10 i_datain <= {`HALT, 11'b000_0000_0000};
//
#10 start <= 1;
#10 start <= 0;
$display("SLL,SRA,SLA,SRL");
$display("pc: id_ir :reg_A:reg_B:ALUo:reg_C:da:dd :w:reC1:gr1 :gr2 :gr3 :ddin:exir:mmir:wbir:smdr");
i_datain <= {`SLL, `gr3, 1'b0, `gr1, 4'b0010};
#10 i_datain <= {`SRA, `gr3, 1'b0, `gr3, 4'b0010};
#10 i_datain <= {`SLA, `gr3, 1'b0, `gr2, 4'b011};
#10 i_datain <= {`SRL, `gr3, 1'b0, `gr2, 4'b0001};
//#10 i_datain <= {`HALT, 11'b000_0000_0000};
//
#10 start <= 1;
#10 start <= 0;
$display("LDIH,SUBI,BZ,AND,OR,XOR");
$display("pc: id_ir :reg_A:reg_B:ALUo:reg_C:da:dd :w:reC1:gr1 :gr2 :gr3 :ddin:exir:mmir:wbir:smdr:zf");
i_datain <= {`LDIH, `gr1, 8'b0000_0100 };
#10 i_datain <= {`BZ, `gr3, 4'b0000, 4'b0001 };
#10 i_datain <= {`ADDI, `gr1, 4'b1111, 4'b1111 };
#10 i_datain <= {`AND, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`OR, `gr3,1'b0, `gr1,1'b0, `gr2 };
#10 i_datain <= {`XOR, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`HALT, 11'b000_0000_0000};
#10 i_datain <= {`BZ, `gr3, 4'b0000, 4'b0001 };
#10 i_datain <= {`ADDI, `gr1, 4'b1111, 4'b1111 };
#10 i_datain <= {`AND, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`OR, `gr3,1'b0, `gr1,1'b0, `gr2 };
#10 i_datain <= {`XOR, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`HALT, 11'b000_0000_0000};
#10 i_datain <= {`BZ, `gr3, 4'b0000, 4'b0001 };
#10 i_datain <= {`ADDI, `gr1, 4'b1111, 4'b1111 };
#10 i_datain <= {`AND, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`OR, `gr3,1'b0, `gr1,1'b0, `gr2 };
#10 i_datain <= {`XOR, `gr3, 1'b0,`gr1, 1'b0,`gr2 };
#10 i_datain <= {`HALT, 11'b000_0000_0000};
end
always #5 clock = ~clock;
endmodule

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