Xilinx 升级 Vivado 2014.3 的 FPGA 功率优化

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Course Description
Attending the FPGA Power Optimization class will help you create a more power  efficient FPGA design. This course can help you fit your design into a smaller  FPGA, reduce your FPGA’s power consumption, or run your FPGA at a lower temperature.
In addition, by mastering the tools and design  methodologies presented in this course, you will be able to create your design  faster, shorten your development time, and lower development costs.
Release Date
February 2015
Level
FPGA 2
Training Duration
1 day
Who should attend?
FPGA  designers with intermediate knowledge of HDL and some experience with the  Xilinx Vivado® Design Suite tools
Prerequisites
● Essentials  of FPGA Design course or equivalent knowledge of FPGA  architecture features; the Xilinx implementation software flow and  implementation options; reading timing reports; basic FPGA design techniques;  global timing constraints and the Constraints Editor
● Intermediate  HDL knowledge (VHDL or Verilog)
● Solid digital design background
Recommended
● Designing for Performancecourse
● Basic  FPGA Architecture: Memory and Clocking Resources
Software Tools
● Vivado Design or System Edition 2014.3
Hardware
● Architecture: 7 series FPGAs*
● Demo board:  N/A*
* This course focuses on the 7 series and UltraScale™ architectures. Check with your  local Authorized Training Provider for the specifics of the in-class lab board  or other customizations.
Skills Gained
After completing this comprehensive training, you will know how to:
● Use the Xilinx Power Estimator spreadsheet to estimate your design’s power consumption after synthesis or implementation to build a better power estimate
● Use Power Report in the Vivado Design Suite to estimate your design’s power consumption after implementation has been completed
● Import activity rates to complete a dynamic power estimation and build the most accurate power estimate
● Use the power_opt implementation options to automatically reduce your design’s power consumption
● Use optimum HDL coding techniques and design practices to reduce your design’s power consumption
Course Outline
● Introduction
● FPGA Power Requirements
● Xilinx  Power Estimator Spreadsheet (XPE)
● Lab 1: Power Estimation with XPE
● Vivado Power Analysis and Optimization
● Lab 2: Power Analysis with the Vivado IDE
● Lab 3: Dynamic Power Estimation with the Vivado IDE
● Power  Management Design Techniques
● Power  Optimization of I/O Resources
● 7 Series Power Management Features
● UltraScale Architecture Power Management Techniques
● How  to Solve a Power Problem
● Worse-Case  Thermal Calculations (optional)
● Spartan-6  FPGA Power Management Features (optional)
● Virtex-6  FPGA Power Management Features (optional)
● Power and Temperature Measurement Features (optional)
● Introduction to Partial Reconfiguration (optional)
Lab Descriptions
● Lab 1: Power Estimation with XPE – Estimate the resources required based on the high-level design description. Enter the amount of resources and default activity rates for the design and evaluate the estimated power calculated by XPE.  
● Lab 2: Power Analysis Using the Vivado IDE –  Estimate the design’s power consumption at synthesis and implementation with the Vivado power report. Generate a power report by using vectorless and vector-based mode and export the power report to the Power Estimator.
● Lab 3: Dynamic Power Estimation with the Vivado IDE – Run the post-synthesis functional simulation of the design to generate a switching activity interchange format (SAIF) file. Create a power report with vectorless and vector-based activity information to verify the design's dynamic power consumption.