多谢斑竹, 另外能否帮我看下这段程序大概是什么意思, module U100(A15,A14,A13,A12,RD,WR,TX,RL_SW,RMT_TX,LOC_TX,UART_INT,PRL_TX1,PRL_TX2,PRL_TX3,CLT_TX,RXD4, LCM_E,LCM_RW,RAM_CS,EIN_CS,UART_CS,LOC_RX,RMT_RX,RX,INT0,RXD); input A15,A14,A13,A12; input RD,WR; input RL_SW,RMT_RX,LOC_RX,TX,UART_INT; input PRL_TX1,PRL_TX2,PRL_TX3,CLT_TX,RXD4; output RAM_CS; output LCM_E,LCM_RW,EIN_CS,UART_CS; output LOC_TX,RMT_TX,RX,INT0,RXD; reg LCM_E,LCM_RW,EIN_CS,UART_CS; assign RAM_CS = A15; assign RX = (RL_SW & RMT_RX) | (!RL_SW & LOC_RX); assign RMT_TX = TX & RL_SW; assign LOC_TX = TX & !RL_SW; assign INT0 = !UART_INT; assign RXD = (PRL_TX1 & PRL_TX2 & PRL_TX3 & CLT_TX & RXD4); always @(RD or WR or A15 or A14 or A13 or A12) begin case ({A15,A14,A13,A12}) 4'b1010: begin LCM_E = !WR; LCM_RW = 1'b0; EIN_CS = 1'b1; UART_CS = 1'b1; end 4'b1011: begin LCM_E = !RD; LCM_RW = 1'b1; EIN_CS = 1'b1; UART_CS = 1'b1; end 4'b1100: begin LCM_E = 1'b0; LCM_RW = 1'b1; EIN_CS = 1'b1; UART_CS = 1'b0; end 4'b1110: begin EIN_CS = 1'b0; LCM_E = 1'b0; LCM_RW = 1'b1; UART_CS = 1'b1; end default: begin LCM_E = 1'b0; LCM_RW = 1'b1; EIN_CS = 1'b1; UART_CS = 1'b1; end endcase end endmodule |