我用MAX+plus II manager 综合的时候出现了一个问题，only one clock enable singal can be defined for a flipflop 什么意思谁能提醒一下。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY second1 IS
PORT(clk, set, reset : IN STD_LOGIC;
s1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sec : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
ensec : OUT STD_LOGIC);
END;
ARCHITECTURE one OF second1 IS
BEGIN
PROCESS(clk,reset,set,s1)
BEGIN
IF reset = '0' THEN sec<="00000000";
ELSIF set = '0' THEN sec<=s1;
ELSIF clk'EVENT AND clk='1' THEN
IF sec=59 THEN sec<="00000000" ;ensec<='1';
ELSE sec<=sec+1; ensec<='0';
END IF;
END IF;
END PROCESS;
END;
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