AHDL Function Prototype和VHDL Component Declaration中的声明 参数不一致 VHDL, Prototype, Declaration, Component, Function

graduate

AHDL Function Prototype (port name and order also apply to Verilog HDL):
FUNCTION lpm_add_sub (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0], add_sub, clock, aclr, clken )
   WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION, ONE_INPUT_IS_CONSTANT, LPM_PIPELINE, MAXIMIZE_SPEED,
        USE_WYS )
   RETURNS (result[LPM_WIDTH-1..0], cout, overflow );
VHDL Component Declaration:
COMPONENT lpm_add_sub
   GENERIC
      (LPM_WIDTH            : NATURAL; -- MUST BE GREATER THAN 0
      LPM_DIRECTION         : STRING   := "UNUSED";
      LPM_REPRESENTATION    : STRING   := "SIGNED";
      LPM_PIPELINE          : NATURAL  := 0;
      LPM_TYPE              : STRING   := "LPM_ADD_SUB";
      LPM_HINT              : STRING   := "UNUSED" );
 
   PORT (dataa, datab           : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        aclr, clock,            : IN STD_LOGIC := '0';
        clken, add_sub          : IN STD_LOGIC := '1';
        cin                     : IN STD_LOGIC := 'Z';
        result                  : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        cout, overflow          : OUT STD_LOGIC );
 
END COMPONENT;
怎么 AHDL Function Prototype和VHDL Component Declaration中的声明 参数不一致？(见datasheet)

应该以哪个为准呢  ？？

caopengly

你应该分析其模块的关系，找到顶层关系接口，然后使用顶层的接口

如function一般只是表达函数关系时调用，在数字电路实现中的单位是模块

我初步估计，应该是

 ORT (dataa, datab           : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        aclr, clock,            : IN STD_LOGIC := '0';
        clken, add_sub          : IN STD_LOGIC := '1';
        cin                     : IN STD_LOGIC := 'Z';
        result                  : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
        cout, overflow          : OUT STD_LOGIC ); 
 

graduate

但他有这么一段介绍：

Altera-specific parameter. You must use the LPM_HINT parameter to specify the USE_WYS parameter in VHDL Design Files. Specifies whether to construct an optimized accumulator with the data from the result[] port that cannot be merged with any other logic. Values are "ON" and "OFF". If omitted, the default is "OFF". For Cyclone, Cyclone II, HardCopy Stratix, Stratix, and Stratix GX designs, if you turn on the add_sub port, this parameter setting must be "ON". This parameter is available for Cyclone, Cyclone II, APEX II, HardCopy Stratix, Mercury, Stratix, and Stratix GX devices only.

使用需要使用 add_sub port，参数 USE_WYS  必须存在的呀？

caopengly

You must use the LPM_HINT parameter to specify the USE_WYS parameter in VHDL Design Files

说用LPM_HINT parameter 确定USE_WYS parameter。

具体的你在琢磨琢磨，因为我得到的信息不多。

graduate

"LPM_HINT parameter 确定USE_WYS parameter。"就是这个问题,既然LPM_HINT parameter 确定USE_WYS parameter,那USE_WYS parameter。参数必须存在才好设置呀!而

COMPONENT lpm_add_sub
   GENERIC
      (LPM_WIDTH            : NATURAL; -- MUST BE GREATER THAN 0
      LPM_DIRECTION         : STRING   := "UNUSED";
      LPM_REPRESENTATION    : STRING   := "SIGNED";
      LPM_PIPELINE          : NATURAL  := 0;
      LPM_TYPE              : STRING   := "LPM_ADD_SUB";
      LPM_HINT              : STRING   := "UNUSED" );
 
   PORT (dataa, datab           : IN STD_LOGIC_.....................

中没有这个参数的描述,所以应该不对,除非刚好设置的参数和这个默认值一致