 MJlM9TYI.rar (312 Bytes)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all; ENTITY fft4_vhd_tst IS
END fft4_vhd_tst; ARCHITECTURE fft4_arch OF fft4_vhd_tst IS
-- constants
constant clk_period : time := 10 ns;
constant clk_stb : time := 2us;
-- signals
file inv :text is in "bar.in";
--file outv:text is out "bar.out";
SIGNAL t_sig_clk : STD_LOGIC ;--:= '0';
SIGNAL t_sig_start : STD_LOGIC;
SIGNAL t_sig_Re_in : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_Im_in : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_Re_out : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_Im_out : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_finish : STD_LOGIC;
COMPONENT fft4 PORT (
clk : in STD_LOGIC;
start : in STD_LOGIC;
Re_in : in STD_LOGIC_VECTOR(15 downto 0);
Im_in : in STD_LOGIC_VECTOR(15 downto 0);
Re_out : out STD_LOGIC_VECTOR(15 downto 0);
Im_out : out STD_LOGIC_VECTOR(15 downto 0);
finish : out STD_LOGIC );
END COMPONENT;
BEGIN
i1 : fft4 PORT MAP (
-- list connections between master ports and signals
clk => t_sig_clk, start => t_sig_start,
Re_in => t_sig_Re_in, Im_in => t_sig_Im_in,
Re_out => t_sig_Re_out, Im_out => t_sig_Im_out,
finish => t_sig_finish); init : PROCESS
-- variable declarations
variable li,lo:line;
variable clk,start: std_logic;
variable Re_in,Im_in : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
-- code that executes only once
READLINE(inv,li);
READ(li,clk);
READ(li,start);
READ(li,Re_in);
READ(li,Im_in);
t_sig_clk <= clk;
t_sig_start <= start;
t_sig_Re_in <= Re_in;
t_sig_Im_in <= Im_in;
wait for (clk_period - clk_stb);
--write(lo,now,left,8);
--hwrite(lo,count,right,3);
--writeline(outv,lo);
wait for clk_stb;
if(endfile(inv)) then
wait; -- 只执行一次
end if;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
--t_sig_clk <= not t_sig_clk ;
wait for clk_period/2 ;
END PROCESS always;
END fft4_arch; 上面的测试代码有什么错误呢??附件中文件是 bar.in | 
