[求助]请各位帮忙,如何解决以下VHDL编译时出现的警告信息
- UID
- 164507
- 性别
- 女
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[求助]请各位帮忙,如何解决以下VHDL编译时出现的警告信息
我用DSP-Builder建立模型,转换VHDL后经编译出现以下警告信息: 1.Warning (10036): Verilog HDL or VHDL warning at DSPBUILDER.VHD(4364): object "svcc" assigned a value but never read 2.Warning: Resynthesizing Cyclone or Stratix WYSIWYG primitives into Cyclone II WYSIWYG primitives; however, resynthesized WYSIWYG primitives may not produce optimal compilation results. 3.Warning: Found 14 output pins without output pin load capacitance assignment 4.Warning: Found pins functioning as undefined clocks and/or memory enables 最重要的是第3个,不知道什么原因,如何解决。我在modelsim仿真,输出波形为零,可能和第3个有关。请各位高手帮忙,在此先谢谢了 |
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- UID
- 164507
- 性别
- 女
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