Started : "Check Syntax for Peasant_Mutiplier".
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* HDL Compilation *
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Compiling vhdl file "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" in Library work.
Entity <peasant_multiplier> compiled.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 23. Type of REGclr is incompatible with type of Reset.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 23. Type of Result is incompatible with type of REGout.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 24. Type of CLK is incompatible with type of CLK.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 24. Type of CLR is incompatible with type of Reset.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 24. Type of D is incompatible with type of A.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 25. Type of CLK is incompatible with type of CLK.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 25. Type of CLR is incompatible with type of Reset.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 25. Type of D is incompatible with type of B.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 29. Type of Clk is incompatible with type of CLK.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 30. Type of Start is incompatible with type of Start.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 30. Type of CLK is incompatible with type of clk.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 30. Type of Reset is incompatible with type of RESET.
ERROR:HDLParsers:800 - "D:/EE4305/Project2/Peasant_multiplier/Peasant_multiplier.vhd" Line 30. Type of Done is incompatible with type of DONE. Process "Check Syntax" failed
我所有的signal都是用bit或者bit_vector。。。package Mult_Components 里的 signal格式也都检查过没错。。 可是还是出现上面的错误.... 下面是主程序code.... library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity peasant_multiplier is
port (A, B: in BIT_VECTOR(3 downto 0);
Start, CLK, Reset: in BIT;
Result: out BIT_VECTOR(7 downto 0);
Done: out BIT);
end Peasant_multiplier; architecture Structure of Peasant_Mutiplier is use work.Mult_Components.All;
signal ASR, BSR, ADDout, MUXout, REGout: BIT_VECTOR(7 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0'; signal High: BIT := '1';
signal F, OFL, REGclr: bit;
begin
REGclr <= Reset; Result <= REGout;
SR1 : ShiftN port map(CLK=>CLK,CLR=>Reset,LOAD=>Init,SH=>Shift,DIR=>Low ,D=>A,Q=>ASR);
SR2 : ShiftN port map(CLK=>CLK,CLR=>Reset,LOAD=>Init,SH=>Shift,DIR=>High,D=>B,Q=>BSR);
Z1 : Check port map(X=>ASR,F=>Zero);
A1 : Adder8 port map(A=>BSR,B=>REGout,Cin=>Low,Cout=>OFL,Sum=>ADDout);
M1 : Mux8 port map(A=>ADDout,B=>REGout,Sel=>Add,Y=>MUXout);
R1 : Register8 port map(D=>MUXout,Q=>REGout,Clk=>CLK,Clr=>REGclr);
F1 : SM1 port map(Start=>Start,CLK=>clk,LSB=>ASR(0),STOP=>Zero,Reset=>RESET,Init=>INIT,Shift=>SHIFT,Add=>ADD,Done=>DONE);
end Structure;
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