caopengly

1.Warning (10036): Verilog HDL or VHDL warning at DSPBUILDER.VHD(4364): object "svcc" assigned a value but never read

svcc没有使用。提示而以。
2.Warning: Resynthesizing Cyclone or Stratix WYSIWYG primitives into Cyclone II WYSIWYG primitives; however, resynthesized WYSIWYG primitives may not produce optimal compilation results.

WYSIWYG 的使用提示可能不能优化。
3.Warning: Found 14 output pins without output pin load capacitance assignment

有14个脚的负载电容有问题，你可以换一下引脚，或者不管它
4.Warning: Found pins functioning as undefined clocks and/or memory enables

你没有设定全局时钟，本论坛上有解决方法。