function signed_sub (a,b:std_logic_vector) return std_logic_vector is
variable a_ext,b_ext :std_logic_vector((a'high+1) downto 0);
variable diff :std_logic_vector((a'high+1) downto 0);
begin
a_ext <= a(a'high)& a; b_ext <= b(a'high) & b; -- 符号扩展
diff <= a_ext - b_ext;
return diff((a'high+1) downto 1);
end function;
上面对于 一个信号
signal a,b :std_logic_vector((a'high+1) downto 0);
调用 sum<=signed_add (a,b);是正确的
但是在对于 截位后的 a,b 信号，使用
sum<=signed_add (a(WORD_WIDTH-2 downto WORD_WIDTH/2-1),b(WORD_WIDTH-2 downto WORD_WIDTH/2-1));却发生错误，大家谈谈怎么设计这个子函数，才能使其有通用性呢？ | 
