状态机示例 示例, 状态

graduate

-- State Machine with Asynchronous Reset、

library ieee;
use ieee.std_logic_1164.all;

entity stmch1 is
port(clk, in1, rst: in std_logic; out1: out std_logic);
end stmch1;

architecture behave of stmch1 is
type state_values is (sx, s0, s1);
signal state, next_state: state_values;
begin

process (clk, rst)
begin
if rst = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process (state, in1)
begin
-- set defaults for output and state
out1 <= '0';
next_state <= sx; -- catch missing assignments to next_state
case state is
when s0 =>
if in1 = '0' then
out1 <='1';
next_state <= s1;
else
out1 <= '0';
next_state <= s0;
end if;
when s1 =>
if in1 = '0' then
out1 <='0';
next_state <= s0;
else
out1 <= '1';
next_state <= s1;
end if;
when sx =>
next_state <= sx;
end case;
end process;
end behave;
在网上找到的一个状态机代码如上
感觉next_state <= sx;好像多于的
因为 case中对每种情况的 next_state 多做了赋值
这样写不知道有什么好处？

caopengly

"在网上找到的一个状态机代码如上
感觉next_state <= sx;好像多于的
因为 case中对每种情况的 next_state 多做了赋值
这样写不知道有什么好处？"

从开始的这段程序中，我们可以看到系统使用的reset为异步复位state <= s0;，但是在没有异步复位时state为随机值，就有可能是sx，这时sx就会等待。相当于default状态。

process (clk, rst)
begin
if rst = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;