| [求助]用VHDL语言分配引脚
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mpc860 is
port (
sysclk: in STD_LOGIC;
clkout: out STD_LOGIC;
cs5: in STD_LOGIC;
cs6: in STD_LOGIC;
cs7: in STD_LOGIC;
st: out STD_LOGIC;
rw: in STD_LOGIC;
ddir: out STD_LOGIC;
rst: in STD_LOGIC;
dena: out STD_LOGIC;
speed: in STD_LOGIC;
pb30: in STD_LOGIC;
pb31: buffer STD_LOGIC;
hreset : buffer STD_LOGIC;
d: out STD_LOGIC_VECTOR (15 downto 0)
);
attribute LOC : string;
attribute LOC of ddir : signal is "P7";
attribute LOC of hreset : signal is "P13";
attribute LOC of clkout : signal is "P38";
attribute LOC of sysclk : signal is "P6";--------ok
attribute LOC of cs5 : signal is "P26";--------ok
attribute LOC of cs6 : signal is "P24";--------ok
attribute LOC of st: signal is "P29";--------ok
attribute LOC of cs7 : signal is "P25";--------ok
attribute LOC of rw : signal is "P39";--------ok
attribute LOC of rst : signal is "P33";--------ok
attribute LOC of dena : signal is "P5";--------ok
attribute LOC of speed : signal is "P22";--------ok
attribute LOC of pb30 : signal is "P27";--------ok
attribute LOC of pb31 : signal is "P28";--------ok
attribute LOC of d : signal is "P8,P9,P11,P12,P14,P18,P20,P19,P40,P42,P43,P44,P1,P2,P3,P4";
end mpc860;
architecture mpc860_arch of mpc860 is
signal num:std_logic_vector(12 downto 0);
signal clk,dir:std_logic;
begin
clkout<=sysclk;
ddir<=rw;
hreset<=not rst;
dena<=cs5 and cs6 and cs7;
process(hreset)
begin
case hreset is
when '0'=>d(15 downto 0)<="0000011001100000";
when '1'=>d<="ZZZZZZZZZZZZZZZZ";
when others=>null;
end case;
end process;
process(speed,pb30)
begin
if(pb30='1')then
pb31<='1';
elsif(speed'event and speed='1')then
pb31<='0';
end if;
end process;
process(sysclk)
begin
if(sysclk'event and sysclk='1')then
num<=num+1;
end if;
end process;
st<=((not pb31)or num(11))and cs5;
end mpc860_arch;
在xilinx 的foundation 下 有程序如上 用attribute LOC 分配编译后注有-----OK的是分配正确的 其他都错了，急切想知道原因 望各位同仁提出宝贵建议。
[em18]
[此贴子已经被作者于2004-3-9 15:51:35编辑过] | 
