- UID
- 82412
- 性别
- 男
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我调试一段例程;却提示出错,请各位高手指点;
-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY limit IS
PORT
(
a: IN STD_LOGIC_vector(7 downto 0);
q: OUT INTEGER RANGE 0 TO 255
);
END limit ;
ARCHITECTURE behave OF limit IS
BEGIN
PROCESS (a)
variable asd: STD_LOGIC_vector(7 downto 0);
bEGIN
asd:=a;
for i in 0 to 7 loop
if (asd(i) = '1') then
next ;--注:错误处?
end if;
q<=1;
end loop;
END PROCESS;
END behave ;
;
编译提示:line29:a next or an exit statement is supported only in an
uncondintional loop
我用的是max+plus2,
不知那里错了,请高手执教;
谢谢。
我改为无条件循环,却又提示另外的错误
-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY limit IS
PORT
(
a: IN STD_LOGIC_vector(7 downto 0);
q: OUT INTEGER RANGE 0 TO 255
);
END limit ;
ARCHITECTURE behave OF limit IS
BEGIN
PROCESS (a)
variable asd: STD_LOGIC_vector(7 downto 0);
variable i: INTEGER RANGE 0 TO 8;
bEGIN
asd:=a;
loop ---for i in 0 to 7 loop
if (asd(i) = '1') then
next ;
end if;
i:=i+1;
q<=1;
end loop;
END PROCESS;
END behave ;
编译提示:object kind unconditionalloop does not have attribute qsym;
in getattr(qsym).
请问各位高手我该如何调适? |
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