我写了一个HDB3码的解码程序，进行simulator时没有输出波形，不知道怎么回事，急！
请各位大侠帮忙指点，我用的MAXPLUS2进行编译仿镇的
我的reset设置 一直为“1”
data_p 000001000101000010
data_n 100010000010100101
clk T=100ns
simulator以后输出
loss data_out ;的结果都为0
原代码如下：
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity dehdb3 is
port(reset: std_logic;
clk:in std_logic;
data_p,data_n:in std_logic;
lossut std_logic;
data_outut std_logic;
data_in_errorut std_logic
);
End entity dehdb3;
Architecture behav of dehdb3 is
signal temp_p: std_logic_vector(4 downto 0);
alias pretemp_p: std_logic_vector(3 downto 0) is temp_p(4 downto 1);
signal temp_n: std_logic_vector(4 downto 0);
alias pretemp_n: std_logic_vector(3 downto 0) is temp_n(4 downto 1);
signal predata_out: std_logic;
signal or_pn: std_logic_vector(4 downto 0);
alias preor_pn: std_logic_vector(3 downto 0) is or_pn(4 downto 1);
signal data_error: std_logic;
signal loss_number: integer range 0 to 63;
signal loss_state: std_logic;
signal n: integer range 0 to 4;
Begin
data_in_error<=data_error;
data_out<=predata_out when (reset='1' and data_error='0') else
'X'; --当reset='1'和收到错误码时输出不确定值"X"
process(clk)
begin
if(rising_edge(clk)) then
if(temp_p(4)='1' and temp_n(4)='1') then
data_error<='1';
else
data_error<='0';
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(data_p='0' and data_n='0') then
if(loss_number=63) then
loss<='1';
loss_number<=0;
else
loss<='0';
loss_number<=loss_number+1;
end if;
else
loss<='0';
loss_number<=0;
end if;
end if;
end process;
process(clk)
begin
if (rising_edge(clk)) then
for i in 1 to 4 loop
temp_p(i)<=temp_p(i-1);
temp_n(i)<=temp_n(i-1);
or_pn(i)<=temp_p(i-1) or temp_n(i-1);
end loop;
temp_p(0)<=data_p;
temp_n(0)<=data_n;
or_pn(0)<=data_p or data_n;
end if;
end process;
process(clk)
begin
if (rising_edge(clk))then
if n/=0 then
n<=n-1;
predata_out<='0';
elsif ((temp_p="10001" or temp_n="10001")and or_pn="10001") then--遇到"1000
1"译码为"10000"
n<=4;
predata_out<='1';
elsif ((pretemp_p="1001" or pretemp_n="1001")and preor_pn="1001") then--遇
到"1001"译码为"0000"
n<=3;
predata_out<='0';
elsif (temp_p(4)='0' and temp_n(4)='0') then
n<=0;
predata_out<='0';
elsif (temp_p(4)='1' or temp_n(4)='1') then
n<=0;
predata_out<='1';
end if;
end if;
end process;
end behav;
ut std_logic;
data_out