| module redlight(clk,reset,out);
input clk,reset;
output [16:1] out;
reg [16:1] out;
reg [4:1] counter;
always @(posedge clk or posedge reset)
if(reset)
counter<=0;
else
begin
counter=counter+1;
if(counter<18)
begin
case (counter)
5'd0 : out<=16'h0001;
5'd1 : out<=16'h0002;
5'd2 : out<=16'h0004;
5'd3 : out<=16'h0008;
5'd4 : out<=16'h0010;
5'd5 : out<=16'h0020;
5'd6 : out<=16'h0040;
5'd7 : out<=16'h0080;
5'd8 : out<=16'h0100;
5'd9 : out<=16'h0200;
5'd10: out<=16'h0400;
5'd11: out<=16'h0800;
5'd12: out<=16'h1000;
5'd13: out<=16'h2000;
5'd14: out<=16'h4000;
5'd15: out<=16'h8000;
5'd16: out<=16'hffff;
5'd17: out<=16'h0000;
default: out<=16'h0000;
endcase
end
else
counter<=5'd0;
end
endmodule |
