在EDK里边加了一个ICON和ILA核,出问题了,哪位高手能帮忙诊断下. ILA, ICON, EDK, 高手, 诊断

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在EDK里边加了一个ICON和ILA核,出问题了,哪位高手能帮忙诊断下.EDK是9.1.02i版.chipscope pro是9.1.01i版本

IPNAME:plb_v34 INSTANCE:plb -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chippro
_video_capture_rev_1_1\system.mhs line 101 - 2 master(s) : 2 slave(s)
IPNAMEpb_v20 INSTANCEpb -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chippro
_video_capture_rev_1_1\system.mhs line 110 - 1 master(s) : 4 slave(s)

Check port drivers...
WARNING:MDT - INST:ppc405_0 PORT:C405CPMTIMERRESETREQ
CONNECTOR:ppc405_0_C405CPMTIMERRESETREQ_to_chipscope_ila_0 -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\system.mhs line 69 - floating connection!
WARNING:MDT - INST:ppc405_0 PORT:C405DBGMSRWE
CONNECTOR:ppc405_0_C405DBGMSRWE_to_chipscope_ila_0 -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\system.mhs line 68 - floating connection!
WARNING:MDT - INST:and_gate_0 PORT:Res CONNECTOR:vid_dec_rst -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\system.mhs line 249 - floating connection!
ERROR:MDT - INST:system PORTIXEL_CLOCK CONNECTORIXEL_CLOCK -
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\system.mhs line 43 - connection cannot be read
internally from entity/module!
This creates an illegal HDL description. Declare an intermediate connector of
a name other than the port name, and assign this to the output.

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
**********************************************
**********************************************
Created elaborate directory

ERROR:MDT - chipscope_icon_0 (chipscope_icon) - Generating the core :
chipscope_icon_0....
Chipscope Core Generator Error :

ChipScope Pro Core Generator
Version : 9.1.01i
Build : 09101.7.12.910

Reading arguments from file
E:/doc/V2P_CD/Reference_Designs/edk_7_1_builds/video_capture_rev_1_1/pal/chip
pro_video_capture_rev_1_1/implementation/cs_coregen_chipscope_icon_0.arg
Warning: Arguments from file will override command line arguments

Creating EDIF Netlist
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1/implementation/chipscope_icon_0_wrapper/\icon_1.edn
Component Name: icon_1
Device Family: Virtex2P
Control port count: 1
Enable BSCAN instance: false
BSCAN chain: USER1
Enable JTAG global clock buffer: true
Enable unused BSCAN ports: false
Force RPM Grid Usage: no
Resource Utilization Estimate LUT:97 FF:28 BRAM:0

Warning: EDIF Netlist being generated

Post Processing EDIF netlist
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1/implementation/chipscope_icon_0_wrapper/\icon_1.edn

Generating constraints file
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\implementation\chipscope_icon_0_wrapper\icon_1.ncf
WARNING: Default charset GBK not supported, using ISO-8859-1 instead

Please verify that the MHS Parameters for "chipscope_icon_0" core are valid
and the generated Chipscope Core Generator arg file :
"implementation/cs_coregen_chipscope_icon_0.arg" is valid
*************************************************************
while executing
"error "Generating the core : $params(INSTANCE)....
Chipscope Core Generator Error :
$err

Please verify that the MHS Parameters for \"$params(INSTANC..."
(procedure "::hw_chipscope_icon_v1_01_a::icon_generate" line 91)
invoked from within
"::hw_chipscope_icon_v1_01_a::icon_generate 40094040"
**********************************************
**********************************************
**********************************************
**********************************************
Param values are : INSTANCE chipscope_ila_0 HW_VER 1.01.a C_FAMILY virtex2p C_DEVICE 2vp30 C_PACKAGE ff896 C_SPEEDGRADE -7 C_NUM_DATA_SAMPLES 512 C_ENABLE_TRIGGER_OUT 0 C_DATA_SAME_AS_TRIGGER 1 C_DATA_IN_WIDTH 32 C_DISABLE_RPM 0 C_DISABLE_SRL16S 0 C_RISING_CLOCK_EDGE 1 C_ENABLE_TRIGGER_SEQUENCER 0 C_MAX_SEQUENCER_LEVELS 16 C_ENABLE_STORAGE_QUALIFICATION 1 C_TRIG0_UNITS 1 C_TRIG0_TRIGGER_IN_WIDTH 8 C_TRIG0_UNIT_COUNTER_WIDTH 0 C_TRIG0_UNIT_MATCH_TYPE basic C_TRIG1_UNITS 0 C_TRIG1_TRIGGER_IN_WIDTH
8 C_TRIG1_UNIT_COUNTER_WIDTH 0 C_TRIG1_UNIT_MATCH_TYPE basic C_TRIG2_UNITS 0 C_TRIG2_TRIGGER_IN_WIDTH 8 C_TRIG2_UNIT_COUNTER_WIDTH 0 C_TRIG2_UNIT_MATCH_TYPE basic C_TRIG3_UNITS 0 C_TRIG3_TRIGGER_IN_WIDTH 8 C_TRIG3_UNIT_COUNTER_WIDTH 0 C_TRIG3_UNIT_MATCH_TYPE basic C_TRIG4_UNITS 0 C_TRIG4_TRIGGER_IN_WIDTH 8 C_TRIG4_UNIT_COUNTER_WIDTH 0 C_TRIG4_UNIT_MATCH_TYPE basic C_TRIG5_UNITS 0 C_TRIG5_TRIGGER_IN_WIDTH 8 C_TRIG5_UNIT_COUNTER_WIDTH 0 C_TRIG5_UNIT_MATCH_TYPE basic C_TRIG6_UNITS 0 C_TRIG6_TRIGGER_
IN_WIDTH 8 C_TRIG6_UNIT_COUNTER_WIDTH 0 C_TRIG6_UNIT_MATCH_TYPE basic C_TRIG7_UNITS 0 C_TRIG7_TRIGGER_IN_WIDTH 8 C_TRIG7_UNIT_COUNTER_WIDTH 0 C_TRIG7_UNIT_MATCH_TYPE basic C_TRIG8_UNITS 0 C_TRIG8_TRIGGER_IN_WIDTH 8 C_TRIG8_UNIT_COUNTER_WIDTH 0 C_TRIG8_UNIT_MATCH_TYPE basic C_TRIG9_UNITS 0 C_TRIG9_TRIGGER_IN_WIDTH 8 C_TRIG9_UNIT_COUNTER_WIDTH 0 C_TRIG9_UNIT_MATCH_TYPE basic C_TRIG10_UNITS 0 C_TRIG10_TRIGGER_IN_WIDTH 8 C_TRIG10_UNIT_COUNTER_WIDTH 0 C_TRIG10_UNIT_MATCH_TYPE basic C_TRIG11_UNITS 0 C_
TRIG11_TRIGGER_IN_WIDTH 8 C_TRIG11_UNIT_COUNTER_WIDTH 0 C_TRIG11_UNIT_MATCH_TYPE basic C_TRIG12_UNITS 0 C_TRIG12_TRIGGER_IN_WIDTH 8 C_TRIG12_UNIT_COUNTER_WIDTH 0 C_TRIG12_UNIT_MATCH_TYPE basic C_TRIG13_UNITS 0 C_TRIG13_TRIGGER_IN_WIDTH 8 C_TRIG13_UNIT_COUNTER_WIDTH 0 C_TRIG13_UNIT_MATCH_TYPE basic C_TRIG14_UNITS 0 C_TRIG14_TRIGGER_IN_WIDTH 8 C_TRIG14_UNIT_COUNTER_WIDTH 0 C_TRIG14_UNIT_MATCH_TYPE basic C_TRIG15_UNITS 0 C_TRIG15_TRIGGER_IN_WIDTH 8 C_TRIG15_UNIT_COUNTER_WIDTH 0 C_TRIG15_UNIT_MATCH_T
YPE basic IPNAME chipscope_ila

ERROR:MDT - chipscope_ila_0 (chipscope_ila) -
Generating the Chipscope core :
cs_coregen_chipscope_ila_0....
Chipscope Core Generator Error :

ChipScope Pro Core Generator
Version : 9.1.01i
Build : 09101.7.12.910

Reading arguments from file
E:/doc/V2P_CD/Reference_Designs/edk_7_1_builds/video_capture_rev_1_1/pal/chip
pro_video_capture_rev_1_1/implementation/cs_coregen_chipscope_ila_0.arg
Warning: Arguments from file will override command line arguments

Creating EDIF
NetlistE:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\p
al\chippro_video_capture_rev_1_1/implementation/chipscope_ila_0_wrapper/\cs_c
oregen_chipscope_ila_0.edn
Component Name: cs_coregen_chipscope_ila_0
Manufacturer ID: 1
Core Type: 2
Core Version: v9.1.1
Device Family: Virtex2P
SRL16 Type: SRLC16/E
RAM Type: 16384-bit block RAM
Clock Edge Used for Sampling: rising edge
RPM Usage: enabled
Trigger Output Port: disabled
Storage Qualification: enabled
Data Same as Trigger: true
Data port is made up of the following trigger ports:
Trigger Port 0
Aggregate Data Width: 8
Data Depth: 512
Enable Gap Recording: false
Enable Timestamp Recording: false
Number of Trigger Ports: 1
Trigger Port 0 Width:8
Number of Match Units: 1
Match Unit 0 Info:
Connection: Trigger Port 0
Type: Basic
Match Counter : disabled
Trigger Sequencer Type : None
External capture : disabled
Force RPM Grid Usage: no
Resource Utilization Estimate LUT:189 FF:175 BRAM:1

Warning: EDIF Netlist being generated

Post Processing EDIF netlist
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1/implementation/chipscope_ila_0_wrapper/\cs_coregen_
chipscope_ila_0.edn

Generating constraints file
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\implementation\chipscope_ila_0_wrapper\cs_coregen_c
hipscope_ila_0.ncf

Generating CDC file
E:\doc\V2P_CD\Reference_Designs\edk_7_1_builds\video_capture_rev_1_1\pal\chip
pro_video_capture_rev_1_1\implementation\chipscope_ila_0_wrapper\cs_coregen_c
hipscope_ila_0.cdc
WARNING: Default charset GBK not supported, using ISO-8859-1 instead

Please verify that the MHS Parameters for
"chipscope_ila_0" core are valid
and the generated Chipscope Core Generator arg file :
"implementation/cs_coregen_chipscope_ila_0.arg" is valid
*************************************************************
while executing
"error "
Generating the Chipscope core :
cs_coregen_$params(INSTANCE)....
Chipscope Core Generator Error :
..."
(procedure "::hw_chipscope_ila_v1_01_a::ila_generate" line 117)
invoked from within
"::hw_chipscope_ila_v1_01_a::ila_generate 40096600"
ERROR:MDT - platgen failed with errors!