[求助]求程序 程序, 求助

bright_fw

各位答人，小弟初学乍练，想求一个计数显示电路（VHDL），键盘接口显示电路（VHDL）。 计数显示电路部分可逆计数电路（10进制）计数最大值256即可，显示电路用三个数码管。最高频率4M； 键盘接口显示电路部分3乘4键盘，0-9和两个功能键（清零，计数）。显示电路三位数码管分别致入。 如果哪位大哥肯帮忙，十分感谢。我的邮箱：BRIGHT_FW@yahoo.com.cn 我做了两个程序，但都是component调用有问题。 计数显示电路： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity countb is port (cp,ec,a,s,clr:in std_logic; qut std_logic_vector(7 downto 0); binut std_logic_vector(3 downto 0); ec0ut std_logic; cy10ut std_logic ); end countb; architecture example of countb is signal count_b:std_logic_vector(9 downto 0); signal p1,p2,rst,dly: std_logic; begin process (cp) begin if ( rst='1')then count_b<="0000000000"; elsif (cp'event and cp='1') then p2<=p1;p1<=a; dly<=count_b(3); if (ec='1') then count_b<=count_b+1; --一时加计? else count_b<=count_b-1; end if; end if; end process; rst<='1'when count_b=10 or clr='1' else '0'; cy10<=not count_b(3) and dly; bin<=(count_b(3)&count_b(2)&count_b(1)&count_b(0)) when s='1'else "0000"; ec0<=p1 and not p2; q<=count_b(7)&count_b(6)&count_b(5)&count_b(4)&count_b(3)&count_b(2)&count_b(1)&count_b(0); end example; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity count_dsp is port (cp,clear:in std_logic; segoutut std_logic_vector(7 downto 0); seloutut std_logic_vector(5 downto 0); numoutut std_logic_vector(3 downto 0) ); end count_dsp; architecture a of count_dsp is component countb port( cp :in std_logic; bin ut std_logic_vector(3 downto 0); s :in std_logic; a :in std_logic; clr :in std_logic; ec :in std_logic; ec0 ut std_logic; q ut std_logic_vector(7 downto 0); cy10 :out std_logic ); end component; signal bin : std_logic_vector(3 downto 0); signal dbs : std_logic_vector(5 downto 0); signal dbm : std_logic_vector(5 downto 0); signal dbh : std_logic_vector(5 downto 0); signal ec0 : std_logic; signal enb : std_logic_vector(2 downto 0); signal bcd : std_logic_vector(3 downto 0); signal clr : std_logic; signal cys,cym,cyh : std_logic; signal s : std_logic_vector(2 downto 0); signal num : std_logic_vector(3 downto 0); signal seg : std_logic_vector(6 downto 0); signal sel : std_logic_vector(5 downto 0); begin connection:block begin U0:countb port map(cp,dbs,enb(0),clr,ec0,cys); U1:countb port map(cp,dbm,enb(1),clr,cys,cym); U2:countb port map(cp,dbh,enb(2),clr,cym,cyh); clr<=clear; selout<=sel; segout(6 downto 0)<=seg; segout(7)<='0'; numout<=num; end block connection; free_counter:block signal q : std_logic_vector(24 downto 0); begin process(cp) begin if cp'event and cp='1' then q<=q+1; end if; end process; s<=q(15 downto 13); sel<= "111110" when s=0 else "111101" when s=1 else "111011" when s=2 else "110111" when s=3 else "101111" when s=4 else "011111" when s=5 else "111111"; enb<= "001" when (s=0 or s=1) else "010" when (s=2 or s=3) else "100" when (s=4 or s=5) else "000"; bin<= dbs when enb="001" else dbm when enb="010" else dbh when enb="100" else "0000"; end block free_counter; binary_bcd:block begin bcd<="0000" when bin=0 else "0001" when bin=1 else "0010" when bin=2 else "0011" when bin=3 else "0100" when bin=4 else "0101" when bin=5 else "0110" when bin=6 else "0111" when bin=7 else "1000" when bin=8 else "1001" when bin=9 else "1111"; end block binary_bcd; select_bcd:block begin num<= bcd; end block select_bcd; sevent_segment:block begin seg<= "0111111"when num=0 else "0000110"when num=1 else "1011011"when num=2 else "1001111"when num=3 else "1100110"when num=4 else "1101101"when num=5 else "1111101"when num=6 else "0000111"when num=7 else "1111111"when num=8 else "1101111"when num=9 else "0000000" ; end block sevent_segment; end a; 可以给我指点一下，或是给我一个例程都十分感谢。[em17]