新手求助：希望各位大侠帮忙啊，有关package的问题 package, 新手, 大侠, 求助, 帮忙

freeman111

我在我的VHDL代码中自己编辑了一个package，结果在编译的时候出现如下错误信息，从而无法继续编译下去：
info:Compliling package "coeffs"
error:unknown problem in e:\vhdl practice\11\fir.vhd [%DLS-E-NoSuchAtrr,Object kind unconditionalLoop does not
have attribute qSym;in GetAttr[qSym].]
其中coeffs为我编译的package名，e:\vhdl practice\11\fir.vhd为我源代码存储路径。
希望各位指出是什么原因造成的啊？

教材上这样描述package的，我不能理解：用户自己定义的package，编译后会自动存放在work库中，我在哪里可以找到这个work库呢？需要用户自己定义吗？

freeman111

我的代码如下：（功能是实现FIR滤波器，编译的时候出现上述错误，希望各位前辈指点，急用啊！！！） library ieee; -----定义存放系数的包 use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package coeffs is type coef_arr is array (0 to 16) of signed (8 downto 0); constant coefs:coef_arr:=( "111111001","111111011","000001101","000010000","111101101","111010110","000010111","010011010", "011011110","010011010","000010111","111010110","111101101","000010000","000001101","111111011", "111111001"); end coeffs; library ieee; --定义fir实体 use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.coeffs.all; entity fir is port(clk,reset:in std_logic; sample:in signed(7 downto 0); resultut signed(16 downto 0)); end fir; architecture beh of fir is begin fir_main:process type shift_arr is array (16 downto 0) of signed (7 downto 0); variable tmp,old:signed (7 downto 0); variable pro:signed (16 downto 0); variable acc:signed (16 downto 0); variable shift:shift_arr; begin reset_loop:loop for i in 0 to 15 loop shift(i):=(others=>'0'); end loop; result<=(others=>'0'); wait until clk'EVENT and clk='1'; if reset='1' then exit reset_loop; end if; main:loop tmp:=sample; pro:=tmp*coefs(0); acc:=pro; for i in 15 downto 0 loop old:=shift(i); pro:=old*coefs(i+1); acc:=acc+pro; shift(i+1):=shift(i); end loop; shift(0):=tmp; result<=acc; wait until clk'EVENT and clk='1'; if reset='1' then exit reset_loop; end if; end loop main; end loop reset_loop; end process; end beh; library ieee; --定义测试平台 use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity testfir is end testfir; architecture testbeh of testfir is signal clock,reset:std_logic; signal instream:signed(7 downto 0); signal outstream:signed(16 downto 0); component fir port(clk,reset:in std_logic; sample:in signed (7 downto 0); resultut signed(16 downto 0)); end component; for filter:fir use entity work.fir(beh); begin filter:fir port map(clk=>clock,reset=>reset,sample=>instream,result=>outstream); clockgen:process begin clock<='1'; loop wait for 50 ns; clock<=not clock; end loop; end process clockgen; po_reset:process begin reset<='1'; wait for 102 ns; reset<='0'; wait; end process po_reset; stimulus:process begin instream<="00000000"; wait for 302 ns; instream<="00000010"; wait for 302 ns; instream<="00001000"; wait for 302 ns; instream<="10100000"; wait for 302 ns; assert false report "--end of simulation--" severity error; end process stimulus; end testbeh;