LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pulse IS
END pulse;
ARCHITECTURE pulse_gen OF pulse IS
COMPONENT test
PORT (clk : IN STD_LOGIC;
cp : OUT STD_LOGIC);
END COMPONENT;
CONSTANT clk_cycle : TIME :=250 ns;
SIGNAL test_clk , test_cp : STD_LOGIC;
BEGIN
U0 : test PORT MAP (clk => test_clk,
cp => test_cp);
PROCESS
BEGIN
test_clk <= '0';
WAIT FOR clk_cycle/2;
test_clk <= '1';
WAIT FOR clk_cycle/2;
test_cp <='0';
WAIT FOR clk_cycle;
test_cp<='1';
WAIT FOR clk_cycle*7;
END PROCESS;
END pulse_gen;
WAIT FOR编译的错误是 unsupported feature error:condition clause and timeout clause together in a wait statement is not support |