| LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test2 IS
PORT (x,y : OUT STD_LOGIC) ;
END test2;
ARCHITECTURE behav OF test2 IS
BEGIN
x<= '0', '1' AFTER 200 ns,'0' AFTER 400 ns,'1' AFTER 450 ns, '0' AFTER 500 ns,
'1' AFTER 550 ns,'0' AFTER 600 ns,'1' AFTER 650 ns,'0' AFTER 700 ns;
y<= '0','1' AFTER 100 ns,'0' AFTER 200 ns, '1' AFTER 300 ns ,'0' AFTER 450 ns,
'1' AFTER 550 ns ,'0' AFTER 650 ns;
END behav;
帮我看一下这个小程序，为什么编译会错误。
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还有：TRANSPORT sig AFTER t1 语句是不是有延时作用。我好像有这个语句与没有用时效果一样？
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH;
ENTITY dff_first IS
PORT ( clk : IN STD_LOGIC;
q : OUT STD_LOGIC);
END dff_first;
ARCHITECTURE dff1 OF dff_first IS
BEGIN
PROCESS (clk)
VARIABLE tmp:STD_LOGIC:='0';
BEGIN
IF clk='1' AND clk'EVENT THEN
--AND clk'LAST_VALUE = '0' THEN
q<=NOT tmp ;
tmp:=NOT tmp;
END IF;
END PROCESS;
END dff1;
----------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH;
ENTITY muxdff IS
PORT (clk : IN STD_LOGIC;
cp,cp1 : OUT STD_LOGIC);
END muxdff;
ARCHITECTURE mux_dff1 OF muxdff IS
COMPONENT dff_first
PORT(clk : IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;
SIGNAL u: STD_LOGIC_VECTOR(0 TO 3);
SIGNAL v,h : STD_LOGIC;
BEGIN
dff_1: dff_first PORT MAP (clk,u(0));
g1: FOR i IN 1 TO 3 GENERATE
dff_1:dff_first PORT MAP (u(i-1),u(i));
END GENERATE;
v <= u(3);
cp1<=TRANSPORT u(3) AFTER 2.2 us;
PROCESS (v)
BEGIN
h<=NOT v;
cp<=h;
END PROCESS;
END mux_dff1;
谢谢！ |
